pingOfDoom

say again?

@TorbjørnT. But doing that i get stuff like "Page iv of 9" at the bottom

also im using the article class and not a book class

Guys I have question that ive looked on the latex stackexchange for but no luck. I wanted to implement roman numbering for front matter and regular numbering for the rest of the report. But the twist is that I want to have the page numbering at the bottom show like i of iv for the front matter and 1 of 9 for the main stuff

Like it just depends on the implementation?

So theres no definitive answer?

But that wouldnt be possible in a structural implementation since the compiler would has a set specification that it needs to implement onto the FPGA

Because the CAD tool can optimize place and routing for a given algorithm

Between structural and behavioural HDL implementations, am I correct in assuming that behavioural would be more efficient in terms of resource usage for FPGAs?

that links me to the Sum line on a full adder

Followed by the file path

verbatim

ERROR: at 60 ns(10000): Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation can not advance in time because signals can not resolve to a stable value in File

any ideas?

on a full adder

and I get some weird error where it says something to do with a zero delay oscillation

Im trying to run a simulation with isim on xilinx ise

Im back with another vhdl question

hello again all

like data.value = x

Like I want to initialize a component without needing a control signal. I want to do something akin to whats possible in c where you can access data members of a struct

@ThePhoton Also is it possible to access the signals in a component without needing to go through an input port

@ThePhoton I dont know how

also

if I have a ROM module that im reading input from, is it possible two port map two different instances of the ROM and be able to change the values inside each ROM?

does anyone know if its possible in vhdl to instantiate a module twice but with different values?

ohhh ok

oh is it that it charges and discharges so quickly

why is that the case?

i mean in the general case

why do we short circuit capacitors when we do an ac analysis?

i dont follow

but i dont fully understand why we have to add them for amplifier models

like i understand that when you have a source theres going to be some resistance associated with it, so you add a resistor there

when we look at circuit models for amplifiers?

This isnt the place to ask a quick question about writing style right?

When we speak of causality of a system, why do we say that systems that are defined for negative time are non causal?

I was just wondering how I would compute the fourier series of (-1)^m * impulse(n-2m) over m from -infinity to infinity

ooh thats unfortunate. thanks anyway!

@ted can i interest you in a question about fourier transforms?

over a summation of m from -inf to +inf

Hello all. Can someone help me with fourier analysis? How do i find the fourier series representation of (-1)^n * impulse(n-2m)

@TedShifrin Yes indeed!

ohh k

which is something i am very ashamed of as an engineer

tbh no

i dont follow

like ok so if you do it graphically, then you have a bunch of lines representing the constraints that you draw and the feasible region is the region bounded between the axes and all of the of lines

but why cant the optimal exist in the space below tho?

guys i had a question about constrained optimization. why does it always work out when doing simplex method that the optimal solution is always a corner point solution?