Reading and writing of parallel I/O is accomplished through the port data registers
(PTxD). The direction, input or output, is controlled through the input enable or output
enable registers.
After reset, all parallel I/O default to the Hi-Z state. The corresponding bit in output
enable register (PTxOE) or input enable register (PTxIE) must be configured for output
or input operation. Each port pin has an input enable bit and an output enable bit. When
PTxIEn = 1, a read from PTxDn returns the input value of the associated pin; when