Reading and writing of parallel I/O is accomplished through the port data registers
(PTxD). The direction, input or output, is controlled through the input enable or output
enable registers.
After reset, all parallel I/O default to the Hi-Z state. The corresponding bit in output
enable register (PTxOE) or input enable register (PTxIE) must be configured for output
or input operation. Each port pin has an input enable bit and an output enable bit. When
PTxIEn = 1, a read from PTxDn returns the input value of the associated pin; when

In rare cases, the I bit may be cleared inside an ISR, after clearing the
status flag that generated the interrupt, so that other interrupts can be serviced without
waiting for the first service routine to finish. This practice is recommended only for the
most experienced programmers because it can lead to subtle program errors that are
difficult to debug.

When enabling the IRQ pin for use, the IRQF will be set, and
must be cleared prior to enabling the interrupt. When
configuring the pin for falling edge and level sensitivity in a 3V
system, it is necessary to wait at least cycles between clearing
the flag and enabling the interrupt.

Setting register PORT_IOFLTn can configure the filter of the whole port, etc. set
PORT_IOFLT0[FLTA] will affect all PTAn pins.