I just buy gold-flash Hirschmann leads. Couple Euro, no work. Couple test clips of several kinds, probably also Hirschmann, big bag of crocodile clips, no need for anything else
For some applications I wanted to try these parrot clips, but they are even more expensive, and it looks like you can't fix the banana plug with a screw in them
does anyone know if its possible in vhdl to instantiate a module twice but with different values?
if I have a ROM module that im reading input from, is it possible two port map two different instances of the ROM and be able to change the values inside each ROM?
@ThePhoton Also is it possible to access the signals in a component without needing to go through an input port
Like I want to initialize a component without needing a control signal. I want to do something akin to whats possible in c where you can access data members of a struct
@pingOfDoom In Verilog, you'd just give different parameters each time you instantiate the module. I expect it's very similar in VHDL.
For initialization, in Verilog, I'd put the initializing code inside the module, but use a parameter to tell it what value to initialize to.
Most Verilog simulators (ModelSim, etc) will let you "reach down" into a module and read or force a signal, but I'm not sure if that's a feature of the Verilog language or a convenience offered by the simulator.
