02:03
@ThePhoton right, but my confusion is this
assume you have a four layer board, two inner layers are power plane and ground plane respectively
you have the PGND and AGND pours on top, according to their layout
if you do thermal vias directly from the PGND pour section, you're connected directly to AGND
so, it would imply that you need to make the layer 2, under the IC at least, a PGND pour itself
but then because you don't want those high power traces going over plane splits, you have to extend the PGND plane to allow it follow all the way until the traces stop or connect to the internal power plane layer
making your AGND internal plane far less contiguous and unbroken
at least that is how I'm seeing it / understanding it