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abdullah kahraman
abdullah kahraman
07:22
Thank you TI for making BLDC stall detection feature a fail..
user image
ti.com/lit/ds/symlink/drv8308.pdf
 
4 hours later…
rdtsc
rdtsc
11:29
Silicon eratta... gotta love it (not really.) I once built an AMD computer, had a nasty full-screen video scrambling issue. Tried everything - replaced video card, PSU, RAM, hard disk, then motherboard... nothing helped. Then I checked the CPU stepping (silicon revision) and found my particular CPU listed a full-screen video bug. Sure enough, replacing the CPU (whole new computer at that point) fixed the video issue.
 
3 hours later…
rdtsc
rdtsc
14:31
Uh oh... expect tons of questions soon about adding $99 "AI Sticks" to Raspberry Pi's... mouser.com/new/Intel/intel-neural-compute-stick-2/…-‌​newproducts--
 
5 hours later…
tigrou
tigrou
19:46
Hello. I have found following verilog code in a tutorial (which map a 4 bit value to a 7 segment display) :

always @(*)
case(BCD)
4'h0: SevenSeg = 8'b11111100;
4'h1: SevenSeg = 8'b01100000;
...
endcase
Both SevenSeg and BCD are registers.
What is the point of setting muxer result (the case statement) in a register if it is not done upon on a clock signal ? could SevenSeg be a wire instead ?
The Photon
The Photon
@tigrou Declaring a signal as a reg doesn't mean it will be implemented as a register.
It only means "I am going to assign to this signal in an always block".
Since SevenSeg is being assigned in an always block, it must be declared as reg.
It's a requirement of Verilog syntax and has nothing to do with whether the code will infer a register or combinatorial logic.
tigrou
tigrou
OK. Thanks for the explanation.
In hardware (no HDL) does it ever make sense to set a reg continously ? (eg : a simple RS flipflop, no clock signal)
tigrou
tigrou
20:11
Well forget what I said :)

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