@JimmyHoffa yeah, actually it's more complicated than that; depending on whether your CPU uses integrated graphics, you'd use either FDI or DMI, but think of them as just really fast (ultra low latency and extremely wide lanes for data flows) buses
that's actually a terrible oversimplification
and I made a terminology error there
for something to be a bus, it has to involve a wire or set of wires that are electrically shared among multiple components, meaning those components all compete for time sending signals down that/those wire(s)
but QPI and later (including the DMI/FDI things) are all point to point interfaces
they are not buses, because there is no physical sharing of electrical contacts between devices, because each PCI Express lane gets its own "wire"
"wire" is kind of a dated term because the interconnects are so tiny, but you get the idea
if your HDD wants to write a bunch of data at the same time that your CPU wants to send your GPU a huge texture, the CPU and PCH do not have to schedule an interleaving of I/O events down a shared electrical contact (a bus) for that to happen
for FSB architectures (Core 2 and older), they do
of course, your SATA controller may have internal contention if you have lots of HDDs attached to it, it may have to schedule each hard drive, but eventually the SATA controller connects to the PCH by way of PCI Express, and the lane(s) it consumes are dedicated to that SATA controller - no GPUs or video capture cards or network cards sharing it
dedicated all the way to the CPU
but yeah, DMI/FDI 2.0 with a PCH is the architecture they've been using since Sandy Bridge, up through Ivy Bridge and the current Haswell
that means for example, an X58 chipset and Nehalem CPU (like an i7-920) would be using QPI, which is the step in between the FSB and the PCH
but starting with the Core i{3,5,7}-{2,3,4}[0-9]{3} line, you're getting DMI/FDI 2.0 connected to a PCH
the tendency of late has been to eliminate classical points of contention within the hardware architecture and provide more direct contact between peripherals and pins on the CPU