« first day (2043 days earlier)      last day (2897 days later) » 
00:00 - 22:0022:00 - 00:00

10:09 PM
the slew rate is literally helping me limit the gain in the mid-stages
i love it
i will have terrible phase issues but I don't really care about that in my application
 
@KyranF I just hybridised all our full discrete ideas
 
oooo
i had no luck on the N-JFET "first option" drawing you made bt
btw*
 
hm. I haven't used JFETs for 10 years either
:/
 
i might have been missing a critical resistor or something, and as-drawn it wasn't doing anything
i played around with it a little but couldn't get any huge breakthroughs so i moved on
 
@KyranF any insights on currents and/or voltages at several nodes?
Anyway
 
10:22 PM
i am liking the cost and behaviour of my current processing chain so i'm going to do the 2nd order channel-select filter and an envelope detector and then finally the comparator
The circuit is gone now, but I had ~3uA from the photodiode, producing 15mA through the NJFET and PNP pair
but all the current was going down into the NJFET and my PNP load resistor never got any significant current, so it sat at 3.3V or whatever
 
@KyranF That is expected behaviour, depending on the size of that resistor
pull out of the base of a PNP and it will conduct, if you made that resistor large, it will hardly create any Collector current
 
yeah
 
And thus go to high
I would have expected Rphoto to be 100's of k's at most in that one and the collector resistor in the 100 ~ 1000 ohm range depending on the PNP
Anyway
 
but how low can one go? I tried 1000 ohms on the collector, plus a few others
 
If you want cuter bias stability the upcoming picture may inspire
Might have to get not a 2N3906
models at gains of 300~700
 
10:31 PM
i'm liking the 2n3906
way better than the 2n4401/3 models i have in my office for breadboarding
 
better is a matter of what you need
There's a reason all those others are still made
 
well yeah in this case, i need the 3906 or similar
of course, i'd not use the 3906 for high power or "Switch" style things but for low current small signals it's great.
 
@KyranF unless it isn't
In the case of option 1, the high gain of the 3906 is exactly what kills power efficiency
I also did the following:.......
BTW, these designs in no way really need a JFET, but I found it fun to keep it in
With the low photo currents the mirror should have a collector voltage no less than 1V under 5V and only mildly variable, which gives you higher bias stability
I really don't think the R and C extra are a good idea, but it's getting late again
So I thought I'd just upload it and let someone else choose
If with some coupling setup there you can reject static currents, you only amplify and transimpede dynamic current signals
 
Why is it that whenever I throw some old junk away I end up needing it 3 months later?
 
but, again, I'm not very happy with it as drawn
Law of conservation of lack of rack space
It's a self-oscillating law
One of the few
 
10:50 PM
Product A:
 
@Asmyldof what's the zener looking thing near the photodiode, connected to the NPN base?
 
@KyranF a zener
 
Product B:
Suspiciously similar?
 
@Asmyldof 6.8V Zener?
 
@ThePhoton artistic coincidence
@KyranF 's what it says
 
10:51 PM
just checkin!
 
Maybe...
This is what I mean:
Zener is just there to make sure the current mirror stays somewhere near its mirror domain
Direct base connection would pull the right collector so low it would wack the whole mirror out of balance
In the "update" it's there to limit the DC peak voltage on the left of the capacitor
Actually, for a .... sort of right setpoint, you'd want:
Though a diode would do
most likely
maybe
Brain stopped
 
11:10 PM
haha
so a current mirror was one way i thought to adventure upon for this challenge
it seems like a good way to avoid loading down the photodiode
 
And had you also thought of rejection of DC current before initial TIA action, I would have slept a lot more this week
:-P
 
11:30 PM
DC current can be cancelled by using an op-amp and trimmer pot going into the non-inverting input of the TIA amp and you can just servo out the DC error, but thats really only for the dark current
by AC coupling the transistor gain stages it would indeed cut out the DC current in general
 
@KyranF Good luck when you work in semi-shaded sunny rooms
I made a guesstimation
For what might be okay
 
yeah.. i mean it could saturate my photodiode but honestly, it's hard enough to get signal out of this thing let alone the sun adding to it
the sun would just increase the DC noise/background level, but all my signal chains are AC coupled to hopefully avoid that
 
Hmz
The sooner you get the current out, before TIA-ing, the less chance you force/shift operation points out of a nice domain
 
i agree
 
the 2M2 ontop the zener would depend on the range of ambient DC interference, as well as the zener itself
 
11:35 PM
aren't zeners bad for leakage though?
 
But you also need a resistor there to allow a wider dynamic
 
and/or they need a huge bias current on the zener to make it act properly
 
Haven't looked at any recently, but I'm sure there's plenty at 6V8 that have less than 100n
All depends on the DC operating point
 
wow, okay
 
But it can also be achieved with two more transistors
Who knows one more with some clever combinating
Anyway, I'm buhbyes
actually
move the zener up, at 4V7, between mirror and cap, set 3 diodes to ground under the resistor, where the zener is now
 
11:39 PM
haha
 
make resistor between 100k and 3M3
 
really, 3 in series?
 
Creates stability for the mirror, allows for a sufficient point of dynamics to divert most of the dynamic current into the transistor base
Maybe 1
Eh
Maths
1:40
 
k, well your thoughts have been super appreciated. go to bed
 
Needs to at least be base voltage, but I think double base
Think I've delivered enough while flying blind (i.e. no maths at any point at all and no sims to build on)
;-)
Good night
 
11:47 PM
G'night
 
00:00 - 22:0022:00 - 00:00

« first day (2043 days earlier)      last day (2897 days later) »