hey guys,what are some reasonable estimates on the latency i should expect from a sensor to a (medium performance) fpga to a another device (in my case a camera).

just trying to do a few order of magnitude calculations to get some basics down

depends on the sensor

If there is no orther processing, maybe 20-50ns

Juggling the SO numbers a bit, if your rep is <10, you are more than twice as likely to ask a question that gets downvoted

@W5VO Also depends on the FPGA speed grade

@W5VO So, we should just not allow users to register when they have less than a 10 rep

electronics.stackexchange.com/questions/237767 I think I am hungry

Very good question (I have it too now), but look at the first line of the first answer... anyone else think this guy should be fired from software development of any kind?

keil.com/forum/57538

Id rather fire that guy who gave back this ticket about a crashing server, which we fixed, and he gave the ticket back so that we make sure that in the future this will not happen again. I have set the ticket to on-hold til 2038

@PlasmaHH That probably makes him think he achieved something. You should find a non-destructive way to make it clear doing that will make bad shit happen

If all other ideas fail, lift up his car, put blocks under the axles that are 3mm higher than his tyres and remove all evidence of something happening (one wheel at a time, to not move it in the space)

See how long it takes before he is able to leave in the evening

he travels via subway...

@PlasmaHH Get a bigger jack....

hm, I almost forgot about that thing:

EPROM burner?

nope, try again

2 x 256 byte EPROM , maybe a little bit of RAM ? an external 1K memory ?

Sony(R) MyFirstExternalLUT(tm) ?

@Marla getting near, no ram though

Which, by the availability of sunlight shading near a window in the picture, is probably blank now

So, actually the answer is: A box of blank nothingness

I win!

. . . the last 512 bytes could be Write Only Memory

@Asmyldof just opened for the photo, I doubt that bit of UV exposure has destroyed more than time lying around, specially since you needed -48V for programming these

@Marla some hint: it is from eastern germany

@PlasmaHH Archive filing system for STASI ?

@Marla by the amount they archived that would be filled in split seconds ;)

of course :)

hello, do you know maybe if PC can detect when monitor is tuned on - I mean do common display interfaces (VGA, HDMI, DisplayPort, etc.) allow for such detection?

so anyone recognizes the gray chips?

grey chips appear to be EPROM 256 byte. Its the white ones I can't identify

@Marla specifically a 1702a, one of the earliest eproms, with a rather horrible interface, compared to today standards. so what did the east block do when they needed some, but couldn't find any?

@PlasmaHH Road Trip ?

LOL

U552 appears to also be an EEPROM, also 256 byte.

dolly?!

Possible DDR knock off of the 1702A

exactly

@mrpyo not ignoring you. I just don't have an answer

So, altogether, 1KByte EEPROM

The question is: For what use?

yes, now it gets more intresting and even harder

@PlasmaHH Boot Loader for PDP-11 (instead of punched paper tape)

@Marla you really think the east block had a pdp?

@PlasmaHH Maybe a quantity of one. You can get all sorts of things on the streets of New York

hehe

Let me translate part of a describing text... "On the ROM modules the user program, written in a special macro language, was stored"

seriously, it is probably the Firmware for early micro-processor system.

but I don't know much about E Germany, so I don't know what small computer (home computer ? ) might exist

nope

I'm trying to figure out what "saldenliste" (a book keeping term visible on the hand written tag) has to do with it.

@JRE what would you probably want to do with such a list in the late 70s?

You'd probably plug it into a special purpose accounting machine.

@mrpyo Yes they can. Or, the interface support that. Whether a specific computer or operating system does, depends on those specific things.

East German Supply/Stock List of Weapons of Massdestruction

@PlasmaHH I keep coming up with "account balance" in translating saldenliste

but why account balance stored in a bulky plug in memory ?

of only 1K

perhaps the secret code - decoder

@JRE yeah

@Marla its macro code, telling the machine how to print data it gets from elsewhere (like a punch card strip thingie)

@PlasmaHH well done Plasma . . I do enjoy a mystery.

BTW, that made me remember when I used a Commodore 64, re-programmed it to be a Print Buffer. It was so annoying back then to have computer unavailable during printing operation.

@Marla more to find here: robotrontechnik.de/index.htm?/html/komponenten/rommodule.htm

it took me a few days of search to find that site or any info about it... am still wanting to know about the code that is in there, but nobody seems to know that macro language

@PlasmaHH it really does seem like an early version of "printer driver"

@Marla more like these report generator programs

OK, so it is an EPROM module for the R1711 or R1720 accounting machine. Cool.

I once had an accounting machine from the 1960s.

Unfortunately, I couldn't do much with it as I only got it after a fire in the school destroyed the print bed and keyboard.

@PlasmaHH I am willing to figure it out, but we'll have to establish a backflow system for the brownie points

I'm off for a bit

byes

Absolute piles of RTL and DTL logic.

Other interesting stats - we (collectively) close about 30% of incoming questions

hm, a bit on the low end, isnt it ? ;)

Stack Overflow closes 12%

probably because a lot of people (like me) are fed up with shit and stop doing anything in the review queues because everyone is insisting we have the wrong attitude and are not needed

aka audits

We have audits on EE.SE?

on SO

ahh... that sounds more right

I mean the idea of audits is ok, but not how it is handled on SO. "so you failed an audit, thats a sign you disagree with the community, so fuck off"

yeah, even the mods are sometimes tripped up by them

the problem is that they are automated

so they better step back and let people handle shit that are in line with the central committee

the problem is that the mechanics is retarded at times (e.g. you can fail close audits without actually doing a close/non-close action) and there is no automated mechanism to appeal, and if you do on meta, they say "oh its allright, just sit it out" but that is not right because your penalties are exponential and there is virtually no cooldown if you properly participate in close vote queue auditing

Hello everybody

anybody knows what positive and negative overfow is?

and/or symetric/assymetric saturation?

@W5VO ?

Morning all

hi

In what context? I can throw out ambiguous terms too...

@trilolil, can we have some context..

W5VO beat me to it

I can try mind reading if you'd like

digital electronics. This is the context: imgur.com/ukKoX45

@BrandenBoucher

@W5VO

@W5VO, tell me what I'm thinking right now.

@BrandenBoucher You want to buy me a sandwich

but you lack my address

shit, that's impressive 0_o

@trilolil, overflow in that case is not electrical but mathematical.

@trilolil Sure, makes sense to me

but I don't know why I care that positive and negative integers overflow at the same absolute value

i would just like to know what the terms pos. and neg. overflow mean

it is written: pos overflow: the sum is replaced by 011...11

what s that supposed to mean

?

@trilolil, in this case, it looks like pos overflow is the overflow of addition on positive numbers.

Do you know what overflow is in a 2's compliment addition is?

negative is the overflow on 2's compliment

@W5VO YEs when both carries are not the same

@W5VO I don t see how this applies to this case

Say you have the same 4-bit math... adding (-4) + (-6) should get you (-10)

yes

but you can't represent (-10) in 2's complement using only 4 bits

indeed

so you have an overflow, and guessing at your terminology, a negative overflow

and that page is about managing the results due to overflow

k

that is what I supposed

but I still don t see exactly

what

the sum is replaced by 011...11

means

Instead of just throwing an overflow flag (e.g. the calculation is garbage), they want the output to be "better behaved"

so instead of getting a positive number from adding two negative numbers, they make the answer the most negative number possible

hmmm

meaning (-4) + (-6) = (-10), but 2's compliment gives you an answer of (+6). The "saturating logic" notices the overflow, and gives the result of (-8) which is the most negative number possible

I have a noise rejection question for a part. Trying to see if I'm reading this correctly. On page 10 of this pdf, it has a graph for PSRR (dB), one with no load and one with a 1k load. It looks like in both cases, it doesn't drop down to 3dB for a while, but those are usually in -dB. ww1.microchip.com/downloads/en/DeviceDoc/20005474B.pdf

and they talk about symmetry in this saturating logic because the most negative 4-bit number is (-8) and the most positive is (+7), and maybe that's also undesirable.

@BrandenBoucher I don't think either drop to 3dB, but I don't think that's relevant for PSRR

@trilolil And the sum being replaced with "011...11" means that you fill the "..." with 1's to make the most positive number that fits in your output. For 4-bits, that would be (0111)

@W5VO so you replace the overflowed number with the most extreme number you can make with your hardware?

@trilolil Yes, preserving the expected sign.

thx that s clear :)

not a perfect solution, and it shouldn't be applied blindly, but that's what they're doing

@W5VO, you're right about reaching the 3dB mark, but is that graph really showing noise rejection or something else?

It's showing the rejection of the input noise. For example, at 120Hz you'd expect about 70-100dB attenuation of your power source

and basically, once you get higher in frequency the regulator can't actually regulate that fast and you end up with decreased performance

or performance that is dominated by the required power supply capacitors

I wouldn't expect it to do a lot of filtering after a 20kHz switch mode supply, for example

@W5VO on wrote on your profile u r a student

@trilolil and?

what kind of student? last year student/PhD?

PhD

what r u researching?

Gate driver design

that s very broad

It's specific enough

and of course there are more details

mhm

I could write a whole dissertation on the topic

@W5VO, ok. Thanks.

;)

I suppose yes

that would be quite unfortunate otherwise

why did u choose to do a PhD?

stupid reasons

ow really? Are you disappointed of having started a PhD?

if yes, why if I may ask

sorry, you may not.

k

it is astonishing to see how many people regret having started a PhD...

I d almost do anything to get accepted to do my PhD

You're at KTH?

nope

another famous univerisyt in another country ;)

in Europe

would you advise me to do a PhD if it is possible?

@W5VO

Have you done any research?

masters?

well I did some pseudo research

any idea what you're getting yourself into?

Currently master student. I did an internship abroad in some space engineering university and had to work with their research team

3 months

I did some pseudo research abroad, almost didn t sleep due to the high workload and loved it

play hard, work hard I guess

@W5VO Then you should sit down and write it instead of mucking around on SE.

@ThePhoton I know

@W5VO Tough love, sometimes Ph.D. students need it.

@trilolil Everybody regrets it, at least for a moment.

Why wouldn t you recommend it?

Why would you regret it?

If you can get out in 5 years, you probably won't regret it long term.

mhm

@trilolil Because you spend your 20's stuck in a lab, doing the will of your advisor, not making much money, not getting much social life, and not moving on with your life.

unless you do it abroad

a whole new culture, working on smth that interests you

btw in Europe you get +/- 2000euro/month as a PhD student

@trilolil With no time to experience that culture.

(depending on the university)

And also in that case with a tough job to pick a fair advisor.

@trilolil IIRC, I got about USD 1000 per month in the mid 90's, which was plenty to live on in the midwest.

I work at night and go to school during the day. So not having much time to "relax" is nothing new to me

In engineering in the US, you will most likely get a stipend for grad school.

mhm

If you want to get a Ph.D. in history or romance languages or something, stipends are harder to come by.

I aint no artist

but a future engineer

What would you recommend me to do in order to maximize my chances to be accepted for a PhD?

knowing my grades are not that high...

@trilolil How much time do you have before applying?

well 1year and a half I think

in September i ll be a master student if everything goes well...

unergrad research: So go work at a specialized company during the vacation?

during 1 month or so?

would that be OK?

@trilolil OK, different system. In the US, most Ph.D. students just apply for a Ph.D. program after undergrad. Masters is just kind of a stop along the way.

mhm

@trilolil That would be good if you can get it. Also give you a chance to compare what kind of work regular graduates and phd graduates do in the real world.

But 1 month is a very short internship. Not a lot of time to do a good project.

@trilolil Does you masters program require a thesis, or just course work?

thesis

Doing a research thesis and having it be a good one would be another positive point when you apply for phd programs.

Or might even get you an invitation from your masters supervisor.

I may do a thesis related to space engineering (as I have some prior experiences in that domain), optics and embedded hard- and software

in Australia I got a bachelors with honours which allows me to skip masters and go straight to PhD

if you dont have honours, you must do masters before eligible for PhD

@ThePhoton What is that? An engineer of some company writing a some sort of request for you to do a PhD?

@KyranF That s not how it works here in Europe...

i found out (from an invitation to go to Aachen and do PhD there) that the europeans basically require a masters

before you can do PhD

^^ exactly

@trilolil No, the professor who supervises your masters work. If s/he also supervises PhD candidates, ...

so in europe it can take 2+ years more to get a PhD than in Australia

oh ok

because you must have masters in the middle

yup

indeed

unfortunately

the only benefit i can see there,

is that at Aachen they have many paid masters research projects going

so you basically "work" for money for 2 years getting experience in a particular area

In the US, masters usually doesn't have any particular industry involvement or industry placement. Although it could have, depending on the school.

and then go into PhD research. so its not that bad, just a delay

@ThePhoton in Australia we have both Masters by "course work" and Masters by research (industry project)

course work is you just do some more courses at uni in a special field

@KyranF Those are both possible here, but I got my masters for basically the first half of my phd work.

Some schools are better than others at connecting up with industry.

Big research schools (MIT, UC, Cornell, ...) are more about phd's and will just treat masters students as junior phd students.

Stanford being a special case.

there's a different mind-set for how PhD/masters students are treated in europe/US compared to Australia

in Australia they are respected, and supported and do their own shit. everywhere else i've heard, they are abused, made to work on random extra stuff unrelated to their goals, and basically used as assistants for everything

so a PhD might take 3 years full time effort on the research topic in AU, but elsewhere, can take 5-6 years because the student is constantly distracted and over-worked on other stuff not related to their thesis

i think the only difference is the students in EU/US are paid for all these distractions

am i wrong? is my sample size of rumours too low?

@KyranF Depends on the advisor.

i think it's the PhD culture which probably various from institution to institution

@KyranF Also the flip side is that in the US system you don't have to already have to be so self-directed at age 24. You can basically work on your advisor's ideas (and if you're brilliant and your advisor isn't an ass, then when you do start to get your own ideas your advisor should let you run with them)

that's true

@KyranF My advisor was really good about only giving me things to do that contributed to my project. But students down the hall spent a lot of time doing data analysis and equipment maintenance for long-running projects that they weren't going to get much credit for.

So in my experience it's more the advisor (and the kind of projects they're working on) than the whole institution.

I mean look at this famous (Australian) experiment:

smp.uq.edu.au/content/pitch-drop-experiment

How many generations of grad students maintained that thing, and how many of them got a publication credit in the end when the drop finally fell?

come on guys who wouldn t want to do a PhD after seeing this: youtu.be/JZux7syGB8E?t=47

haha

that pitch though

love that channel

hey guys, for an active filter op-amp selection, if i have a band-pass filter with 0 gain at pass band, 5MHz signals being processed, what sort of GBWP or -3dB BW values should I be looking at? I'm trying to find real-world op-amps that I can simulate. i think i've been going way too low for my opamps and my results are retarded because of it

is VFB or CFB better for active filter op-amps?

CFB has lower noise i hear

but i don't care about noise ;)

@KyranF How much beyond the pass band do you need to guarantee the stop band?

That first sentenced makes it Sound like "as opposed to a passive opamp filter"

To me, that's a problem for a simulation study. Compare results with two different op-amps, one with 10 MHz GBWP, one with 100 MHz. See if it makes any difference (depending on the criteria for your application).

well, im not expecting to get any signals greater than 5.5MHz

and i'm doing a channel select filter

channels are spaced either 500Khz or 250Khz apart, depending what performance I can get

5.5mhz square wave?

and yes that's a reasonable idea, testing an overly powerful filter op amp and see if it does what i expect, then find a lower one

Plasma, it's a sine-wave of 5Mhz 800mV p-p by the time it gets there

Good, just making sure

@PlasmaHH a passive op-amp filter compared to an "active" one like a multiple-feedback topology filter, why would one choose one over the other?

I need (as far as I can tell currently) a pretty good Q factor and rejection of non-targeted frequencies. I want to have some significant signal if it's the center freq, or very low signal if it's outside of the pass-band.

as a practical example, my 800mV P-P signal should be >= 200-300mV p-p after the filter stage if it's the correct frequency, else it should be very low, like 1/10th that

so i guess i'm aiming for -20dB for the channels that i'm not filtering for. 5MHz filter output should show like ~80mV or less if i pass a 5.5Mhz or 4.5Mhz signal into it. These are the test conditions i'll be using in my simulations