This answer is flat out wrong. Using an individual DDR4 chip (not a DIMM) as an example, the addressing scheme is composed of 18 row bits, 10 column bits, and 4 bank bits yielding a maximum address space of 2^32, or 4,294,967,296 bytes, or 4GiB per chip. Previous versions of DDR had fewer row bits and fewer banks, but DDR has always been designed so that the maximum size is a power of 2.