> For 1y nm 2D planar NAND such as 16 nm or 15 nm MLC/TLC NAND devices, for example, the process integration on the memory cell array and peripheral region comprises well/active/isolation (SA-STI, self-aligned STI) formation; cell FG/CG and peripheral gate formation; and contact and interconnection (metals and vias) formation. Of course, patterning approaches such as DPT (double patterning technology) or QPT (quadruple patterning technology) and an air-gap process for active, wordline and bitline patterns on memory cell array region should also be included for manufacturing 2D planar NAND p…