Discussion between Eggi and oppo

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10:03

Q: How to check receiving 16-bit data using a serial terminal?

I am using an FPGA vhdl UART code to send 16bits of data with a 1 start bit, 1 stop bits and even parity bit. I need to check whether the sent 16bit packets are correctly receiving using a terminal software on windows pc. I did a research on google and found many terminals that only allow for 8 b...

Eggi

How's your code doing? The error probably comes, because x and y can be 0 at the same time. When this happens you would be assigning A and B to tx_data. Check your assignment for y. If you aren't doing anything with x, you can discard y and check for x = '0' then tx_data <= A elsif x = '1' then tx_data <= B and an else.

oppo

@Eggi thank you that error was solved with your help

@Eggi i have updated the code can you check?

Eggi

The problem with your code is: You want the process to process when there is a new rising edge, have a look at some process tutorials. Also, variables are a bit tricky when synthesized. I would recommend to start with simple Signals and discard the variables for now. The code looks bad in a few ways. You are assigning a value to A and reading from A at the same time. You are aware that the old value from A is read before the new value is assigned?

oppo

@Eggi do you think the issue is with if elseif statement? since i have assigned x=1 at end of if loop and the elseif condition check is again x==1 then does it always run elseif and updates tx_data with value B... is this the issue?

Eggi

From what i know, simulation tools update variables at the spot and your process is updated very fast, because there is no clock assigned to the process and i don't see any stimulus for a testbench. My guess is that your simulation tool can't calculate what the current assignment for x is and uses the last entry in the process which would be the elsif statement

Àre you even using a simulation tool?
Or are you testing in hardware?

oppo

10:18

I will let you know the result of replacing all variables into normal signals. I am testing on hardware. I use Altera de0 nano soc FPGA board. to check UART output i use TTL to USB converter and a serial terminal on my PC

Eggi

You are starting with vhdl?
I strongly recommend using a simulation software like modelsim.
They are faster in compiling and a GUI where you can see the signals in relation to your clock is worth gold.

oppo

I set them to signals still I get only 63 on output

Eggi

did you implement something like a clock signal in your process? (rising_edge?)

is this a school project or is this for work?

oppo

10:34

this is a school project

yes i have use rising edge clock after begin of the process

Eggi

so your teacher probably gave you some books/examples?
When installing quartus, modelsim is installed too. Use it. It is simple.

what are you using? Are you reading the value from the terminal on the pc? or are you using something like signal tap?

oppo

i use Hterm terminal

on pc

i get 8 bits values correctly

but i need to pass 16 bit values to PC

Eggi

ok the next thing is, how does your process look now? How often is it updated? Did you implement parity bit and so on?

oppo

the parity is in trasmetter code

for uart part i am using the example given in altera wiki

eewiki.net/pages/…

the uart code is given in above link

process runs on 50MHz clock

Eggi

I'll give you an example testbench code, but you have to find it yourself.
Use modelsim

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity example_bench is
end entity;

architecture tb of example_bench is
component uart IS
-- Use default generics
GENERIC(
clk_freq : INTEGER := 50_000_000; --frequency of system clock in Hertz
baud_rate : INTEGER := 19_200; --data link baud rate in bits/second
os_rate : INTEGER := 16; --oversampling rate to find center of receive bits (in samples per baud period)
d_width : INTEGER := 8; --data bus width
parity : INTEGER := 1; --0 for no parity, 1 for parity

This is called a testbench.
This wraps around your RTL Code and is used for simulation. Not for synthesizing.

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