Any idea on how to generate ramp from clk and trigger like this?

I want to generate this using basic logic gates and maybe transistors, current source

clock sets and trigger resets a SR latch, where Q controls a transistor that shunts a cap that's charged by a constant current source

how can you make sure the ramp is 1V with constant current source?

@Shalvenay

@anhnha ah, didn't see that requirement at first

probably will need to set it up so trigger sets the latch and a comparator resets it at the 1V point

using the !Q output to control the switching transistor

@Shalvenay but 1V should be at the end of cycle

@anhnha right, the transistor is shunted across the cap

@Shalvenay I still don't see how can you do that with a constant current source

@anhnha it'll take as long as it needs to reach 1V, then the comparator will flip the latch, turning ON the shunt transistor and discharging the cap through it

But I need 1V and the end of clock cycle

not just 1V anywhere in between

@Shalvenay

hm. well, you can do it with a clock reset, as long as your clock frequency is fixed and you set your current source so the ramp ends at 1V

but the ramp width is not constant

it changes with time

so the current source value also has to change

I don't see how to change the current source

OK, it seems like you need to take this problem back to the prof, for you have two conflicting constraints going on here :/

@Shalvenay I'm not a student

also what's conflicting constraints here?

@anhnha or well, take it back to whoever gave it to you

@Shalvenay no-one gave me

what's what arise during my design

what's conflicting constraints?

the two termination conditions of 1V and end of cycle....

@Shalvenay it's ONLY conflicting if you use CONSTANT current source!

but I don't have to use constant current source

The only way you can make that work is if you have some way of knowing the width of the pulse before you start the pulse

Otherwise, you don't know how quickly the ramp voltage will rise.

Can you use a microcontroller? If so, then it would be possible to start a loop when the trigger is activated which increments a counter and sets a DAC which is disabled. Let it count up until clock goes high - that is the count at which 1V should be output. Then on every next trigger activation, increment a counter and set a DAC which is enabled and scaled for 0-1v output.

Reset when count = max length.