Can someone explain to me why the current flows as shown in the left diagram? I thought it would flow like it does on the right one that I made i.imgur.com/29Jd5aG.png
I'm thinking the only way that would happen is if the current of V1 is much bigger than V2, but it doesn't say that anywhere in the example
I now see that later on they show V2 = .5*V1, so if V2 = V1 the current would flow like the diagram on the right?
ahh, now it shows that I2 should be flipped the way I have it. But they still have the original I3. Can someone explain that?
@ZachSaucier When you're doing a circuit analysis, you can just make an initial guess about the current direction. If you guessed wrong, when you solve the circuit you'll just get a negative number for that current.
Say I have 1-5 MB of data in an FPGA, and I want to get it out to a PC over an ethernet connection as quickly as possible (say, in less than 1 s). What kind of uP/uC and what interface to the FPGA could make that happen?
@jippie Let's not assume I'm limitted to 10M ethernet.
And also I realize if I have, say, 100M ethernet, I'm not going to get more than maybe 50 Mb/s. Or maybe 5-6 MB/s. But how can I make the ethernet be the bottleneck, and not the interface between the FPGA and whatever's controlling the ethernet?
