@Justme, could you tell me which position of the ESD would be helpful?

@Kartman, I am trying to protect the PHY chip

@Justme, yes I would need PoE support

Am I correct in understanding that it is not correct to move the TVS diode (DBI) from the PHY side of the transformer to the RJ45 side? I feel that it is not right, based on the resistance value and capacitance of the capacitor between the transformer and RJ45 specified in the Hardware Check List @LuC

TVS on the media side would seem to invite short-circuit currents on hot-plugging. Putting it behind the transformer introduces some impedance (leakage inductance, resistance), and possibly saturation if the transient has long duration. Clamping voltage then is more critical as there's little impedance between TVS and PHY. Probably using a low-clamping snapback diode such as Semtech makes would be advisable.

@TimWilliams, thank you for your comment. So, you suggest to place the TVS in the location indicated in the app note itself, right? Also, is this TVS Diode OK? semtech.my.salesforce.com/sfc/p/#E0000000JelG/a/2R0000001TBb‌​/…

I generally agree with the appnote, yes. That's probably an adequate TVS, yes. Oh, was your PHY a GbE style (H bridge output, no VCC bias to centertap) (see datasheet Fig.1)? You'll need a higher nominal voltage rating if 10/100 style (CT wired to VCC).

@TimWilliams, LAN8740A is the PHY. Also, is the part that I suggested fine?

Yes, I saw that.

@TimWilliams

Is that TVS part fine?

Was the PHY wired GbE style (H bridge output, no VCC bias to centertap) (see datasheet Fig.1)?

Just confused

the PHY is not GbE

right?

ww1.microchip.com/downloads/en/DeviceDoc/…

The IC is wired as shown in page 3 of the above document

Look, I get you want a quick answer. I'm just confused that, you are apparently unable to make a simple comparison, between the TVS datasheet's Fig.1, and the circuit that you've evidently been toiling away at for the last several months?

Could you explain me where I am wrong? Or what I am misunderstanding

I'm not sure how much clearer I can get. What do you have [will you have, if not made yet] connected to the PHY side center taps?

PHY side centre taps are connected as shown in the page 3 of the checklist document that I shared in the chat link above.

I am sorry if I am not conveying properly

They show VDDA wired to CT>

Yes

VDD is synonymous with VCC.

OK

So what would you conclude from that fact.

There is Vcc bias from centretap

Correct. And then?

So the PHY is wired in GbE style

that does not seem to follow from the "GbE style (no VCC bias to centertap)"

Vcc bias from centrerap is there right?

"There is Vcc bias from centretap" as you say

yes

sorry

Extremely sorry

Got mixed up

It does not follow from GbE style

Are you there @TimWilliams

Correct

So how do we go ahead from there