I am working with a CD4029BE on a breadboard. The connections are as follows:
VDD to +12VDC
VSS to ground
The clock input receives a 3Hz 0 to +12V clock pulse
J1-J4 are shorted together, and then shorted to ground
Pin 5 (Carry in) to ground
Preset Enable shorted to ground
Up/Down and Binary/Decim...
You could have occasional double clocking. Slow or noisy clock edges can cause two clocks on the positive edge or a false clock on the negative edge. What does your clock look like?
You must generate your clock from a clean source, like an oscillator, or a switch debounce buffer. Using a plain switch will generate many extra pulses, giving you the symptoms you see.
@Mattman944 I will post an image of my clock. It is a 0 - 12V signal coming from a 555. The pulse width of the clock is about 27-28 ms, with about 50% duty cycle. I do not see any clock irregularities. Currently I have my pin 3 (555 output) shorted to the clock input of the 4029.
@StainlessSteelRat how do you determine what bypass cap to use "close" to the chip? I tend to try values starting small and then going larger until I see something that works. Any recommendations?
We need to see this clock with a 500ns/div timescale. Two captures are needed: one of the rising edge, another of the falling edge. Also, decoupling caps for both 555 and 4029 can be just 0.1uF, connected directly across the supply input pins. Nothing bigger is needed, just maybe 10uF-100uF bulk capacitor between the voltage rails on the breadboard. Tweaking the capacitors beyond that won't improve things. Post a picture of the breadboard so that we can see all the connections. Most likely the breadboard layout is goofy. I've put together your circuit and it works fine. So the idea is ok.
We also need to see an accurate schematic of your circuit. For example, is there a capacitor between VC and GND on the 555 chip? Are pins 2 and 6 connected together? Etc. The breadboard pictures must be good enough to trace all the connections, otherwise we can't check your work.
Now that I have verified that CD4029 binary counter can count 1 MHz square wave signal, with stable 50% duty cycle, next step is to use a low frequency signal perhaps 10Hz (The OP uses 3Hz), and see if the O/P duty cycle is stable. I know NE555 timer module's signal is not easy to set at very low frequencies, so I will be using the XY PWM sign gen to do the testing: How can Rpi4B python UART talk to XY PWM Signal Generators? - Asked 2 years, 10 months ago, Viewed 979 times raspberrypi.stackexchange.com/questions/104779/…
ICL8038 vs NE555 sig gen. I fund it annoyingly awkward to adjust the NE555 module to get a 3Hz test signal used by the OP. The reason is that the duty cycle and frequency cannot be independently adjusted. So for preliminary testing, I am using the ICL8038 sig gen for easy parameter adjustment. Only after satisfactory experiment, I will then go back to NE555 for final testing.
Discussion on question by Thomas Wilk…
Discussion on question by Thomas Wilk…