last day (16 days later) » 

DKNguyen
DKNguyen
23:43
the FF clock is on the input side though isn't it?
so woujldn't the originating clock domain still have control of the signal as it drops into the other domain?
oh, you're not tonyM
I'm waiting for him
TonyM
TonyM
He might not be...but I am :-) Good evening...
DKNguyen
DKNguyen
hi
TonyM
TonyM
So you've got a 32-bit data bus that we can call 'bus' and let's say we're going from a 100 MHz CLKA domain to a 10 MHz CLKB domain.
DKNguyen
DKNguyen
ok
TonyM
TonyM
The ADFFs launching data will each connect to BDFFs latching data. CLKA and CLKB are asynchronous (not off the same PLL). Each DFF pair can/will have a different path delay between them. So on a CLKB, a BDFF might latch a just-changed data bit, an about-to-change bit or a changing bit (go metastable).
(sorry so slow, typing on my phone)
DKNguyen
DKNguyen
23:55
Oh so the synthesizer can't enforce timings in the path between ADFF output and BDFF input
I think I get it
sort of like the synthesizer has no timing data to work with in that path so it can't check anything
or timing reference rather
TonyM
TonyM
Not that I know of. But also, the IC can't provide paths that are that precisely equivalent for all those bits, across temperature etc.
DKNguyen
DKNguyen
it's not as big a problem going from slow to fast, right?
TonyM
TonyM
What I did in a design I had was use handshaking to get them across.
DKNguyen
DKNguyen
how did the handshaking work?
TonyM
TonyM
Spot on: slow to fast is easier and the bigger the ratio the easier.
DKNguyen
DKNguyen
23:59
but yeah, you're on phone so maybe no point typing it all out
unless you have a blackberry that can type fast

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