Machines like the DEC PDP-6 or PDP-10 had a "hardware read-in mode" for paper tape, triggered by a toggle on the console. This was capable of reading in a papertape reading program, which then read the rest of the papertape. Hardware readin mode was NOT ROM, but it performed a similar function in the general scheme of things.

Read in modefor the PDP-6 could actually start a program residing in core locations 0..15 in core memory. On a machine with fast accumulators, these core locations were shadowed by the accumulators, unless in read in mode. Thus, they were semipermanent. Not ROM, but close.

Does "core rope memory" counts?: en.wikipedia.org/wiki/Core_rope_memory

Also keep in mind that core memory survives loss of power. So early computers basically used core memory as "ROM" - when you turned the computer back on, the OS etc. was still there. If it got corrupted, you'd bootstrap, either by manually entering a short program into the core, or by having core rope/a coldstart panel/some module with it somewhere. But that was a handful of words, often less than a kbit. So "price per kbit" for that wasn't important...

Delay lines are not random access. You have to wait for the bits you want to reach the read head.

@WalterMitty Does it work like bootstrapping Altair 8800, flip-flopping switches on the console and load a tiny tape reading program?

@Vlad Core rope memory had been mentioned. Any other candidates?

@dirkt I guess Japanese PhotoTypesetting(電算写植) would require very large ROM to store dot-matrix or even vector fonts, which I guess would take more than 1Mbits. For example, SAPCOL in the 60s used an PDP-8.

I don't know about "cheapest," But how about IBM's TROS (transformer read-only storage)?

Also, CCROS (Card Capacitor Read-Only Store).

@SolomonSlow TROS had been mentioned. However, I couldn't find anything details of the unit cost, let alone comparing with other kinds of ROMs. Anyway, I do hope it might be the cheapest and easiest to reproduce and could be piled by quantities without using too many tubes or transistors, to cope with the requirements of a CJK glyph font card, before silicone ROM chip is widely available.

So something like mask ROM will be expensive in low volumes but cheap in high volumes, and core rope memory will be the opposite.

Silicon diodes were available and inexpensive by 1969. One could construct a rather slow and power hungry ROM using only two rather beefy transistors per address bit along with a bunch of resistors and diodes. Adding a transistor per word would improve speed while reducing power consumption. If one put the switching logic along the edge of a rectangular grid, one could have a ROM that used the presence or absence of diodes to encode data. Alternatively, for larger memories, one could use four columns for each pair of bits, eight for each group of three, or sixteen for each group of four...

...and then only require one diode for each group of two, three, or four bits. I'm not sure if anyone used this latter approach to save diodes, but it would not have been difficult to do so.

Does it work by flipping switches to enter a program? Sort of. Keep in mind what dirkt said about core memory surviving a power loss. Also keep in mind that, in normal operation, the PDP-6 references fast accumulators for locations 0 through 15. Thus, what ever program is stored in those locations will tend to endure for a long time. Initially, the papertape reading program has to be entered in in binary using the toggle switches.

The hardware readin mode for the pdp-10 was handled by built in logic, not ROM driven. There were seven toggle swithes set to choose the readin device, usually paper tape but possibly DECtape.

From the point of view of replicating a small amount of code in relatively large (hundreds and thousands) series, various forms of TROS and diode arrays on discrete components undoubtedly were in the lead. The former were used for all sorts of microcode, the latter for, for example, generating fonts in early vector terminals. In addition to speed, electrical characteristics also mattered - diode arrays made it possible to minimize additional decoder and amplifier circuits.

@Schezuk The typesetting itself wasn't fully digital until 4th generation devices came up in the late 1980s/early 1990s. 1st generation (1940s) where modified letter linesetting machiens, 2nd generation (1960s) were specialised mechanical machines like Diatype with one font on a glass disk. Third generation (1970s) used the same principle, but now on square glass carriers and controlled by microprocessors. Text was entered with a CRT based editor, much like today, only to be outputted under computer control once done.

@dirkt CO-59(六社協定新聞社用文字コード) contains around 2k characters. It would be still adressable if the word width of the ROM is enlarged to be able to contain a single glyph in one word, say 200 bits or even more. But this is just a guess since I have no idea if this method is PDP-8 compatible or how SAPCOL was implements at all.

@supercat Thank you for informing me of Diode matrix! I have never thought about that before. Can you provide a comparison about the cost effectiveness and scalability on Diode Matrix and Transformer read-only storage?

@Schezuk: I don't know about the latter, but diode matrices allow trade-offs between performance and transistor/chip count. The 1971 video game "Computer Space" used four 256-bit and one 128-bit diode ROM to render the shapes of space ships, though I think the designer was seeking to minimize the number of lit pixels so as to minimize the number of diodes. See github.com/pong74ls/ComputerSpaceSchematics/blob/master/… for a schematic.