QuickishFM

In general BIOS update images will be cryptographically signed by Lenovo meaning you cant change the BIOS to bypass verification or anything. Generally with Thinkpads at least you have to physically flash the EEPROM (on the motherboard with a RasPi or other programmer) with an image to reset the supervisor password, and then load the BIOS back in to then change the password to something new. These BIOS images cost money and its not an easy job. If its under warranty you might want to get it replaced or something. This is of course assuming you own the device nad have proof of purchase

as far as I can see, tying the 2 grounds bypasses any protection for SC/OC/OV the child tp4056 gives, so thats probably not wise to do. However thats assuming the 5V boost IC/circuit shares the same ground as the tp4056, it might not do in which case you might be safe to tie them, but again i wouldn't unless the problem persists using a boost convrter in the child

aside from the 2 different grounds as im still not sure if that'll cause a problem, but hopefully they work OK...maybe you can tie both output grounds together, im not sure if this'll cause a problem yet...more analysis needs to be done on that front but i think this is OK

@JingleBells This looks like itd work

@JingleBells probably will have to, hoepfully it doesnt cause too much issues

@JingleBells Maybe you can include a boost circuit in the master to provide 5V to the child tp4056? Or, like in the circuit you've shown, include both tp4056s in the master

@JingleBells Thats probabbly causing 2 issues at least - loss of charging voltage and the 0.25 issue (maybe). You definitely want each TP4056 input to be 5V - or 4.5 at the very least.

@JingleBells Yeah, that's fair, once it's working you can tweak it to a smaller and more efficient package, yeah

@JingleBells that's OK :) glad you're making progress

@JingleBells that's a good idea, hopefully a higher voltage won't cause child battery to run out too quickly.

I'll be possibly online a bit earlier tomorrow (saturday) but im still setting things up on my windows & linux partitions here so today and yesterday i couldnt just open chrome and check my SE like normal, so was a bit late, sorry :P

That boost converter for 5V should work fine, perhaps you can figure the circuit and build it into your pcb for fixed 5v as that one allows you to change it. If the space gets really small maybe a small 5V boost IC will do the job - of course this is entirely up to the availability and cost of the ICs.

I think it should hopefully work from the new diagram. It seems both sides have their relative supplies 5V from their grounds - so connecting both grounds shouldnt introduce some sort of -0.27 problem

@JingleBells thats ok :) I've seen the diagram youve put, it seems theres a boost converter in the child for the button recognising problem? Thats fine as long as it fits, as you say, though im unsure the implications of connecting 2 5v boosters in parallel once theyre connected.

@JingleBells I think he's meant that as a 5V source but if you boost it it should be the same as itd be 5v still

@JingleBells hmm, i think its something to do with the R3 connected toggling the on/off state of both transistors then...all I can think of as the difference between connected and not connected. Also the presence of load 1 in parallel but we've determined that isnt the case already

Hey sorry dude, I'll be online tomorrow at 12PM onwards BST (i guess 2PM in your area)

@JingleBells hmm, he might be on to something but honestly i dont know how load 1 (parent load) could affect the child load, and even upon disconnecting it there wasnt any change to the -0.2 volts...

@JingleBells This could very well be the case. Are you able to temporarily replace the child battery with a solid 4V or 4.1V source to see if it performs better?

@JingleBells I checked Multisim yesterday and really couldnt reproduce it, i think it mihgt be to do with the fact tha tthe load is modelled as a resistor but might be doing some stuff inside to produce a higher voltage than the transistor emitter, so yeah i've not got a clue on that im afraid

Hello, sorry for disappearing lol, i've got myself a new PC and was putting it together today

no worries dude :)

i've got to go out for a bit but will have a look again later and see if i come across anything new

i think its potentially something in the load thats producing a higher voltage or something

hmm i cant reproduce a negative voltage across the load in Multisim for now... not sure how thats being caused

ok, cool

ahh ok

well your source seems wrong cause a few on google have emitter as arrow in both pnp and npn

Emitter is the arrow side

i.e. the physical emitter pin on the transistor i mean, cause an NPN has a reversed symbol so it might be connected upsdie down

so just to check, you have the emitter of both transistors connected to child out+ right?

so load 1 has no bearing on it then

ahh right

hmm

can you disconnect Load 1 and see if that has any effect?

i see

ok, check voltage across child load pls?

@JingleBells ok, hmm, this seems to be 4.2 of the tp4056 charge voltage, plus the 0.32v that was somehow being generated

yeah just voltage across q1 and q2 for now

Ok nw

@JingleBells so just to confirm, does child out- have +0.32 wrt to stlink gnd?

Ok cool

np :)

coudl you pls let me know the model of transistors you use for q1 and q2? Assuming the resistor values of i.ibb.co/qrywMLc/Capture.png are all accurate

okey dokes i am going to model the circuit in multisim and see if i get anything substantial out of it

this would only occur if the load itself was producing a voltage higher than the 3.7V

so then, the emitter of q1 seems larger than the collector...very strange

and we confirmed this yday where r3 was 3.7V approx

so 0v on q2 means its basically a short - so r1 pulls q1 down fully