Eggi

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Discussion on answer by DenisS: Why a…

Imported from a comment discussion on boardgames.stackexchange...

Eggi

Feb 13, 2020 01:44

Is there a list with common layer misinterpretations somewhere? I am searching for the layer for cost reduction/alternative costs.

Electrical Engineering

A place to talk with friends from the EE community about vacuu...

Eggi

Apr 1, 2019 10:59

The problem is: I need to split the output from one amplifier to several PCBs, if I would take one for each PCB the price of the whole thing would skyrocket.
Currently it looks like that I will use some tvs diodes and control the selection of the voltage drop with jumpers.

Eggi

Mar 29, 2019 08:01

@W5VO I am driving some ink jets which are capacitive. The source of the 130V signal is controlled with a power amplifier, MP104 from apex, but I can't change the behaviour of this part

Eggi

Mar 29, 2019 07:58

@W5VO I have to look further into it, but if possible I want to keep it small

Eggi

Mar 28, 2019 16:37

I have to add, 2 Amps over 2µs

Eggi

Mar 28, 2019 16:35

Hi guys,
I need to design a fixed voltage drop which should be controllable with a µC.
The load where I want to enable/disable the voltage drop is capacitive and the voltage is about 130V. So no programable poti for me.
Do you have an idea?
I thought about diodes, I saw some circuits with thyristors for AC control and resistive load, but I am not too sure if it fits my application.

Eggi

Aug 23, 2018 10:52

Hi,
What are your thoughts about data buffers on PLC slaves?
I just had a conversion where people say that this is not what a "real time" bus (EtherCAT in this case) is meant for. In this application the bus can be asynchron to the output of the slave, where in my opinion a buffer is necessary but its hard to explain and bring arguments when the other site just says: no, real time bus slaves should not need buffers.

Eggi

Aug 22, 2018 15:15

@PlasmaHH Thank you for the clarification. I mean in a world full of acronyms i am not too sure if Vout means the same for everyone.

Eggi

Aug 22, 2018 15:01

hi,
Sorry to bother you, but can someone explain to me what the Vout pin is used for in this regulator?
https://www.diodes.com/assets/Datasheets/AZ1117E.pdf
Is this pin used for the output voltage? What does Pin 2(output) do then?
Are pin output and pin Vout directly connected? Or is this just a heatsink?

Eggi

Aug 17, 2018 11:54

currently the idea is a usb jack with a protection cap but i don't really like it

Eggi

Aug 17, 2018 11:50

the pcb is bare but painted. There is no case. The connector is going to be on the border of the pcb.
I don't want the manufacturer to program the device. I want to be able to program it in the house.

Eggi

Aug 17, 2018 10:37

to add is that the JTAG is used once

Eggi

Aug 17, 2018 10:34

hi guys,
Can you recommend a connector for JTAG? I don't care if i have to build the adapter myself.
I am looking for something in a small form factor for an environment which contains conducting dust.

Eggi

Mar 14, 2018 17:14

always a solution

Eggi

Mar 14, 2018 17:13

what do you think of this preparation?

Eggi

Mar 14, 2018 17:12

Supply voltage varies between 12V and 20V

Eggi

Mar 14, 2018 17:11

there is the idea with n-channel mosfets, but i have no way to place any cap between gate and Source

Eggi

Mar 14, 2018 17:11

Eggi

Mar 14, 2018 17:10

sorry, i wanted to write some text too ^^
Sorry to bother you again, i am trying to replace this circuit, the duty of this circuit is, when sense is grounded that a 3.3V signal is applied to sense_in

Eggi

Mar 14, 2018 17:09

Eggi

Mar 14, 2018 16:20

I give it a try, thanks guys!

Eggi

Mar 14, 2018 16:07

@ThePhoton No, came up 10 minutes ago

Eggi

Mar 14, 2018 15:57

@Asmyldof looks like time for a redesign...

Eggi

Mar 14, 2018 15:48

Hi there,
do you know if there are pnp transistors in a sot 23 package where the collector is on pin 2 and emitter is on pin 3?
As reference i want this one: https://assets.nexperia.com/documents/data-sheet/BC856_BC857_BC858.pdf where pin 2 and 3 are swaped?

Eggi

Feb 1, 2018 08:21

To my JTag problem, i used an USB Blaster where the line receiver was defect, an LV27A and this caused the onchip diode at the TDI pin to short against ground.

Eggi

Jan 31, 2018 14:28

I have to add that this behaviour came out of the blue.
Internally the TDI is pulled against VCC and external the same.
No forced connection against ground.

Eggi

Jan 31, 2018 14:27

Hi guys,
Any experience with #TDI to Ground and zero Ohms?
My FPGA refuses JTag communication and i see that the #TDI Pin is grounded, even when there is no supply.
Do you have any advice for me?

Eggi

Nov 7, 2017 15:21

period

Eggi

Nov 7, 2017 14:56

For maintenance.
20 years are a long time.

Eggi

Nov 7, 2017 14:52

I am searching for a (replacement) for a 168dimm sdram, 256MB with two banks.
Do you know where to get such RAMs? I am in Europe and everywhere i search, they are obsolete or in small numbers (< 20), mostly had a look at the fast distributors like digikey, farnell and co.
100 to 200 pieces would be nice.

Eggi

Nov 7, 2017 14:49

hi guys,

Eggi

Sep 20, 2017 14:12

Hi there,

I am searching for a vertical RJ45 connector for a 1000Base-T application, like this one:
http://www.mouser.com/ds/2/706/fastjack-vertical-gigabit-520346.pdf
Circuit E, where all 4 center taps are seperated and with 0.01µF or 0.1µF connected to ground.
But this one is rather expensive. An additional transformer stage is not necessary.
Can you help me here?
I've seen a few from Wuerth Electronics but horizontal, are the vertical ones the rare ones?

Eggi

Sep 12, 2017 09:44

Thank you.
Do you see any problems with measuring the coil? The GND Potential of the coil and the op-amp are the same.

Eggi

Sep 12, 2017 06:31

Hi guys,
Can you help me with designing a current measurement circuit?
I have a coil with around 100 Ohm, inductance is not known yet, but later on and i had a look at this: http://cds.linear.com/docs/en/datasheet/1366fb.pdf
The sense resistor would be a 30mOhms 1W resistor.
So at 450mAmps (made some measurements, this was the max. current) i have 13,5mV.
The slew rate of the OPAmp is sufficent.
What are things I have to be aware of? The input capacitance of the OPAmp so that i don't hit resonance frequency?

Eggi

Sep 7, 2017 07:26

Sorry, I am searching for a transceiver.
I found an AFBR-59F3Z from Broadcom, but we have a lot of LC cables around and this one has POF, but the size would be ok, but i would prefer a vertical transceiver

Eggi

Sep 6, 2017 07:02

I mean the sfp modules.

Eggi

Sep 6, 2017 07:02

I've seen those lc transceivers used in switches, but they are quite big in size.

Discussion between Eggi and oppo

Imported from a comment discussion on electronics.stackexchang...

Eggi

Dec 7, 2017 10:47

This is called a testbench.
This wraps around your RTL Code and is used for simulation. Not for synthesizing.

Eggi

Dec 7, 2017 10:46

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity example_bench is
end entity;

architecture tb of example_bench is
component uart IS
-- Use default generics
GENERIC(
clk_freq : INTEGER := 50_000_000; --frequency of system clock in Hertz
baud_rate : INTEGER := 19_200; --data link baud rate in bits/second
os_rate : INTEGER := 16; --oversampling rate to find center of receive bits (in samples per baud period)
d_width : INTEGER := 8; --data bus width
parity : INTEGER := 1; --0 for no parity, 1 for parity

Eggi

Dec 7, 2017 10:39

I'll give you an example testbench code, but you have to find it yourself.
Use modelsim

Eggi

Dec 7, 2017 10:36

ok the next thing is, how does your process look now? How often is it updated? Did you implement parity bit and so on?

Eggi

Dec 7, 2017 10:35

what are you using? Are you reading the value from the terminal on the pc? or are you using something like signal tap?

Eggi

Dec 7, 2017 10:35

so your teacher probably gave you some books/examples?
When installing quartus, modelsim is installed too. Use it. It is simple.

Eggi

Dec 7, 2017 10:28

is this a school project or is this for work?

Eggi

Dec 7, 2017 10:28

did you implement something like a clock signal in your process? (rising_edge?)

Eggi

Dec 7, 2017 10:20

You are starting with vhdl?
I strongly recommend using a simulation software like modelsim.
They are faster in compiling and a GUI where you can see the signals in relation to your clock is worth gold.

Eggi

Dec 7, 2017 10:03

Àre you even using a simulation tool?
Or are you testing in hardware?

Eggi

Dec 7, 2017 10:03

From what i know, simulation tools update variables at the spot and your process is updated very fast, because there is no clock assigned to the process and i don't see any stimulus for a testbench. My guess is that your simulation tool can't calculate what the current assignment for x is and uses the last entry in the process which would be the elsif statement

Eggi

Dec 7, 2017 10:03

The problem with your code is: You want the process to process when there is a new rising edge, have a look at some process tutorials. Also, variables are a bit tricky when synthesized. I would recommend to start with simple Signals and discard the variables for now. The code looks bad in a few ways. You are assigning a value to A and reading from A at the same time. You are aware that the old value from A is read before the new value is assigned?

Eggi

Dec 7, 2017 10:03

How's your code doing? The error probably comes, because x and y can be 0 at the same time. When this happens you would be assigning A and B to tx_data. Check your assignment for y. If you aren't doing anything with x, you can discard y and check for x = '0' then tx_data <= A elsif x = '1' then tx_data <= B and an else.