W5VO

I think that just makes it a curiosity that works in your simulator

@DannyuNDos D1, D2, D5 aren't ever going to be forward biased...

The sequence is 1, 1.5, 2, 3... it's something I've seen more with slide rules, otherwise you have a large magnitude gap on a log scale

If you needed only 1.8V at some decent current with only a 12V source, and you stacked a 12V->5V converter with a 5V->3.3V converter, and then added a 3.3V -> 1.8V converter, that would be a lot of DC-DC converters (because you could probably get a reasonable 12V -> 1.8V converter direct). But what if those were the only DC-DC converters that you had in stock and it needed to be done ASAP?

Everything has tradeoffs. In theory you could run a lot of circuitry off one flyback converter if you needed multiple voltages, but that's not always a viable option. I can come up with a lot of scenarios where an extra DC-DC converter is silly, but not universally. A "good" design has many constraints, some of which are impossible to know looking at the final system.

@Lundin Did you get ratioed?

Did SE screw something over and use this as a distraction?

I mean, it's a bit heavy-handed, but I'm not offended by it...

It has to do with how much of the signal the active device is conducting. Class A is 100%, AB is <100% and >50%, B is 50%, and C is <50%.

@misk94555 The description calls it a class AB, which matches the intent of the schematic page that says "Linear Amplifier". Linear amps end at class B. Just looking at the schematic topology it could be anywhere from AB to C depending on the biasing.

If it's not a sealed system, dust/particles can cause scattering that can result in crosstalk, but that's probably something you already considered.

yes, and the ability to calibrate for that matter.

I mean, when it's above the cathode voltage by a diode drop, that's an easy case but probably not what you're saying.

Yeah, you're paying for the nice analog output, a built-in gui / buttons, and a sticker

To be fair, I use them interchangeably as well. Being pedantic about it can be tricky and just not a lot of fun. At one point, the "terminal" was an actual separate piece of hardware (for example, VT100) that connected to a mainframe.

I'd say more like the terminal is what's taking what you type and inputting it into the shell program, which executes your commands

on Linux, the terminal is the software that is acting as a terminal access. The shell is the software that takes commands (e.g. bash, csh, tcsh...)

So cut off the connector? I don't see the hang up.

looks like the next ADC pin can be routed to the negative differential input

Spectre is a common simulator as well (basically the same thing). There's new versions of the transistor models. Other than that, things work basically the same. What's your goal?

Maybe? There's a few things in the circuit that make it look like it's been designed for a few "abnormal" conditions with the power supply.. but I'm not sure that's doing anything other than keeping the emitter resistor at 0.7V

Tricky and diminishing returns over copper. Going from aluminum to copper reduced resistivity by 37%. Going from copper to silver would save only another 5.3% over copper. Honestly I haven't looked at interconnect pain at 2nm to know if that's where a competitive advantage could be formed.

ultimately, when you talk about processing, there's sometimes just enough differences between materials that metal A is very easy, but metal B, in the same periodic column, is hard.

but for silver, it's marginal benefits over copper. Tungsten is a typical barrier layer.

Silver is the devil.

If you were operating it once every 10 seconds, it would last about 10 years.

Practically, when doing IC design, it's hard to get one value that works under every condition on these 0-feedback solutions. It's a good sanity check, and a good goal for a logic library, but hardly a necessary requirement.

@EE18 So in general, the more sophisticated a transistor model you use, the more accurate an answer you will get. The problem is that as your model becomes more and more sophisticated, you find out that there usually isn't one "absolute" answer. There are many cases where you'll find that the "optimal" value depends on your conditions - for example, what is your optimal inverter ratio at your minimum design temperature versus your maximum temperature?

But I'm sure if you take the two IDS equations, set them equal to each-other, and then substitute one of the VGS/VDS values for VDD-VGSn, you'll get there

I haven't written out the equations because I would probably just simulate it to get a closer answer (and because it will probably change over PVT)

Maybe it's possible to make a gate so lop-sided (e.g. MASSIVE NFET, tiny PFET) where the NFET has enough subthreshold drive strength to drive the PFET to VSS, but that seems like a degenerate case instead of an earnest example.

@EE18 Here's my take on your question. If you draw the "virtual circuit" where Vin is tied to Vout, you get a diode-connected NFET and a diode-connected PFET. Those structures are basically guaranteed to be in saturation.

@EE18 If you're at a university, get a hold of your Inter-Library-Loan (ILL) folks - they can often source books (or excerpts from books) for you. At my university, that was a free* service.

Nice, I knew that was on the roadmap at some point... but I didn't know how that was implemented. Selecting from stacked/close objects sucks

Ahh, I missed the sample rate. You're probably fine from that perspective.

or it could be some weird aliasing

Just something to be aware of - you've got ringing in the >100MHz range, and that's a prime suspect to make sure that you're measuring it correctly.

and related question: electronics.stackexchange.com/questions/411399/…

analog.com/en/technical-articles/….

Just as important, but probe compensation is different from what I'm talking about. Your ground clip will have 10nH of inductance, which can form a tuned circuit with the input capacitance (10pF?)

or do you know the resonant frequency of your scope probe with a ground lead?

So as a new user of oscilloscopes, did you use a low-inductance ground connection for that measurement?

A lot of this stuff gets hidden behind NDAs, the one real example that I can give is from SkyWater in their Sky130 open IC design kit - they mention that they have many many AO/OA/AOI/OAI gates (skywater-pdk.readthedocs.io/en/main/contents/libraries/…) in each logic style. Thanks for reopening it.

The subject is not academic, but it only comes up in digital ASIC design. I felt that the op gave an example that they were having trouble with and had given an attempted solution.

@VoltageSpike Why did you close this? electronics.stackexchange.com/questions/692863/…

Probing techniques are also fun to learn about.

Wait - are you trying to get those two holes in the plane to be filled? I wouldn't worry about that.

Why not? You haven't really given any context, and you're probably not charged by the via in this design.

Is there proper amounts of output capacitance? The output is probably a sawtooth at that 5khz frequency, right?