Too bad we don't have a "mostly MDA" configuration dump. Your PC7640 BIOS provides a "mostly CGA" dump, because that one is used to restore a sensible CGA configuration after the panel has been used.
The "mostly MDA" configuration should point to the underline enabling mechanism.
Register 21 is "number of characters shifted per line". If you decrease it, you put only 79 new characters in the panel for a new scanline, so the ex-rightmost charactor did not get pushed out, but gets a second chance to be the leftmost character now.
The multiplex between panel bit 3 and MDA video could be implemented by just evaluating the panel bus width. So no need to control that with a separate bit.
With great help by user Michael Karcher we found the following details poking through the V6366 controller's innards:
# ports
102
VDCS (something about switching to the external monitor?)
3d4
CRTC index port
3d5
CRTC data port
3d8
Mode control register
3d9
Color control register
3da
statu...
I also remembered the Olivetti / AT&T graphics solution. If I remember correctly, saw a laptop using one of the clones in 1992. The 640x400 mode is mainly enabled by a control bit in the Olivetti extra control register at 3de. This obviously conflicts with the Y6366 register assignment.
Did you get around to probe any further bits today?
In the external monitor configuration, the actual CRTC registers are used. In the flat panel configuration, the overriden values are used. Something must switch between the configurations.
The idea of this register being horizontal sync position override makes less sense if we look at the CGA-on-MDA values. F8 would be 78 | 80. But the horizontal sync position for MDA mode should be 52, not 78 according to my documentation.
Yes, just as you write. But you can merge it into a 16-bit write.
The video processor can not do 16 bit writes. That's why it works. The processor sees that the 16-bit write was not accepted and re-writes the top 8 bits to the successive address.
The idea is that (as long as you don't switch monitors), you set up the 3dd/3de registers only once and then updating the CRT registers just does the right thing, even with a flat panel that does not use actual CGA timings.
Actual 5A setting makes no sense for the plasma display, as it only has columns 00 to 59.
But with adjusting it "-4" as you calculated, 56 would be inside the valid range.
It seem to make sense that 31 is intended as "horizontal sync delta" register.
MDA default is 52. CGA default seems to be 5A (and my book is wrong here). CGA-on-MDA uses a F8 in this register, which is -8, exactly what you need to transform the CGA into the MDA value.
Also matches for graphics mode: CGA uses 2D, HGC uses 2E (for 720 pixels). Tulip's CGA emulation uses a delta of -1, which would result in 2C. This is 2 character clocks off the 720-pixel values. (the sync comes 16 pixels early).