In VHDL, a for loop executes in zero time. This means that instead of waiting a clock cycle between each iteration, the entire loop is run within one clock cycle, with only the final result of the loop being shown at the end. This is what's happening in your code. The entire loop is executing in ...

1000BaseT cannot be daisy chained. If you want daisy chain, use 10Base2 (thinnet) or 10Base5 (thicknet). 1000BaseT can be used in star topology and would need a bridge between nodes.

@StaceyAnnRieck's answer is impresively thorough and quite accurate... if I may summarize/clarify the first statement though, the 'for' statement in an HDL simply expresses 'syntactic replication' not 'sequential execution'. That is to say, it simply generates more hardware elements (gates), an...

If this problem doesn't have hard realtime constraints, and it sounds like it doesn't — you just want it to run "faster", then it seems like it might be quite amenable to acceleration on one or more GPUs. There are several software libraries that make this a relatively straightforward proposition...