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12:18 AM
@El'endiaStarman I think I found a serial full adder.
You can't tell which way the wires are going in that picture.
 
Just build it in varlife already. :P
(I'm half-kidding.)
 
If a "tick" represents the time it takes for a single logic gate to process information, then this adder requires input every two ticks.
This is due to the size of the loop it contains (where carry out is fed to carry in).
 
12:49 AM
maybe I should finish my varlife extension-- that way, it would be easier to transmit, store, and create circuits
 
1:12 AM
@PhiNotPi: Got an A AND NOT B gate! :D goo.gl/lswptU
 
hype!
 
There's probably a better one though.
Incidentally, due to the way I built it, you could easily extend it to make a wire crossing that works in both directions, but only passes on one wire if signals come on both at the same time. Which is funny. :P
 
1:28 AM
@El'endiaStarman goo.gl/CvD6Uy
 
@PhiNotPi .....welp. I was that close. >_<
 
 
12 hours later…
1:39 PM
@El'endiaStarman I think I can go ahead and start work on assembling other small circuits.
 
Are you planning on using Logsim? Seems like it'd be hard to simulate series data/adders with that?
 
We need to figure out how we're going to do RAM (both read and write), counters, and the display.
 
Incidentally, we need to come up with a way to store data in series.
 
Delay line memory is a form of computer memory, now obsolete, that was used on some of the earliest digital computers. Like many modern forms of electronic computer memory, delay line memory was a refreshable memory, but as opposed to modern random-access memory, delay line memory was sequential-access. Analog delay line technology had been used since the 1920s to delay the propagation of analog signals. When a delay line is used as a memory device, an amplifier and a pulse shaper are connected between the output of the delay line and the input. The memory capacity is determined by dividing the...
 
@PhiNotPi So, basically just a cycle?
 
1:43 PM
The wireworld computer has a RAM bank that was a set of loops, one for each address. Each word simply circles around its little loop until it is read.
 
The wireworld page: quinapalus.com/wires9.html
We could do a transport-triggered architecture (like wireworld), or we could do something more traditional.
 
I was actually wondering if it's possible to "freeze" signals.
That's something we can do that Wireworld can't.
 
That might be something we could do.
Let's say that we had a signal travelling though a special "freezable wire."
When the wire receives a second signal (applied to its side), it allowed the signal inside of it to flow.
 
1:58 PM
yeah, something like that
It might be easier to have an input wire and an output wire, where the signal gets frozen in between them. That might be harder, now that I think more about it... :P
 
How will we have non-destructive reading?
 
The "naive" approach with freeze-wire means that reading will remove the data from memory.
 
Yeah. I guess we'll have to develop something like a D-latch (or is it S-latch?).
 
that's a D latch, with D for data and E for enable.
 
2:14 PM
Those are NOR gates, right?
 
NAND gates
 
oh, okay
 
except, we would really want to simplify that circuit.
 
yeah
And there's that perennial problem with NOT'd output.
Perennial?
Adjective: perennial ‎(not comparable)
  1. Lasting or remaining active throughout the year, or all the time.
  2. a perennial stream
  3. (botany, of a plant) Having a life cycle of more than two years. Compare annual, biennial.
  4. (figuratively) Continuing without cessation or intermission; perpetual; permanent; unceasing; never failing.
  5. 1790, Edmund Burke, Reflections on the Revolution in France
(5 more not shown…)
Noun: Wikipedia
  1. perennial ‎(plural perennials)
  2. A perennial plant; a plant that is active throughout the year or survives for more than two growing seasons. Compare annual, biennial.
Yay I remembered right!
I think oscillators could be really useful if we figure out the right design. As in, have three inputs (set, read, clear) and one output, which gets a signal only when the oscillator has been set and a read signal has been received.
I wonder if this is brute-forceable.
 
If we built the gate as described above, it would continuously output a stream of 1s when it's set to true. (This requires a clock to generate the additional 1s). If we have a "read" signal, I think we could avoid using a clock.
 
2:24 PM
What I imagine is that a read signal will destabilize the oscillator such that the output wire gets a signal, but then it returns to normal. A clear signal would completely destroy the oscillator.
 
That might be possible, but I don't know how to design it.
 
....brute force, maybe?
Or PPCG challenge? :P
 
The best I could make, with only one NOT gate.
 
D latch?
 
yes
 
2:36 PM
So we just need to design an A XOR NOT B gate?
 
I still think a "read" signal is our best option, and it's similar to what the wireworld computer did.
 
We might be able to do some pretty interesting stuff with a 3x3 square of B2/S.
There are at least four different oscillating patterns, and I've seen one common self-destructing pattern.
 
@zyabin101 I'm removing your straw poll from the starboard because I think we've pretty much settled on series data.
I have so many VarLife tabs open right now.
 
hahaha :P
 
@PhiNotPi Thanks.
I have helped you so much with your poll.
 
2:49 PM
Well, I found a weird structure where an oscillator (including the wire!) is set with a signal that passes through and unsets it on the next pass. :P
...I should build in a URL shortner...
 
room topic changed to The Quest for Tetris: For discussing this: meta.codegolf.stackexchange.com/a/8016/12914 | link to VarLife: play.starmaninnovations.com/varlife (no tags)
actually, I have a better idea for a VarLife link
room topic changed to The Quest for Tetris: For discussing this: meta.codegolf.stackexchange.com/a/8016/12914 | link to VarLife: goo.gl/UQMOYZ (no tags)
oops
room topic changed to The Quest for Tetris: For discussing this: meta.codegolf.stackexchange.com/a/8016/12914 | link to VarLife: goo.gl/9liiDH (no tags)
there, now it links to VarLife with the correct palette.
 
Excellent.
 
3:14 PM
@El'endiaStarman not really what I was aiming for, but a new signal splitter: goo.gl/BpaUpa
 
Haha, sure enough.
 
3:32 PM
How many bits should our computer be?
 
Uhhh...how big of a Tetris field will we have?
8x16 could be handled within 8 bits.
 
It really depends on how big the tetris program will be, since that determines how big our address space will need to be. I reckon that, if we can write a bare-bones Tetris program in X lines of assembly, then we need to prepare our computer to be able to handle programs at least 4 or 5 times as large.
 
yeah, that would make sense
 
Check out this game, it's 1D tetris: kongregate.com/games/zigah111/tetris-1d-2-0
There's a very limited tetris game in ~140 bytes of javascript: gist.github.com/aemkei/1672254
 
3:48 PM
Yeah, those are pretty minimalistic, but definitely stuff we can try on the way.
 
4:17 PM
loop-based memory is probably pretty easy to make
 
Yeah, I guess so. And we can use an AND gate to control when the signal gets passed on.
 
4:44 PM
@El'endiaStarman The loops themselves are simple, but what about addressing?
 
5:23 PM
@m654 hello!
^ full adder schematic
 
oooh
Serial adder, right?
Have you started building it in VarLife?
 
yes, serial. The little loop in the middle right is where the carry is fed back in.
Actually, I just created a double-output XOR gate that can make it simpler.
 
5:40 PM
@PhiNotPi Hi, just checking this chatroom out. That's all
 
For context, we are attempting to program Tetris in Conway's Game of Life.
double-output xor: goo.gl/rcw27b
 
That's cool.
 
^ compressed serial adder
 
oooh
That's definitely doable in VarLife.
That's a 100x80 field though, so simulations will be somewhat slow.
 
Are we standardizing 20x20 gates?
 
5:51 PM
Oh right, we don't have to do 20x20.
What's the biggest gate we have?
The right-angled AND gate is 6x8.
So 10x10 is definitely enough, I think. 50x40 field, then.
Well, a bit more to have the input and output wires.
 
I think we could do 11x11 (centering the wire).
 
oh yeah, that'd be good
Incidentally, the slimmer wire is easy to bend slightly diagonal, and also a little easier to turn corners with, I think.
 
Well, it might be possible to reformulate everything in terms of the thinner wire.
we could do 16x16 gates to work well with the hashlife algorithm.
 
Oh yeah, sure.
Maybe even 8x8.
 
there's no way we could do 8x8, right?
 
6:00 PM
I mean, when I said that the AND gate was 6x8, I was including the output wire.
 
Actually, if the input/output wires are offset from the center, then when we rotate the gates, then the wires won't line up between gates.
Will we having wire padding between everything, or will the padding be part of the gate?
we could do 11x11 gates with 5 cells of wire padding between gates, bringing the total size to 16x16
 
Wire can generally be added/removed as needed, though it is worth noting that the slim wire has to be in multiples of 4.
Ah, your double-output XOR is 8x8 for the gate alone, which doesn't include the bits of wire in and out that are needed.
 
6:33 PM
@El'endiaStarman Working on building an adder in varlife
 
This moment has been a long time coming.
 
Indeed.
 
7:05 PM
@El'endiaStarman Almost done!
 
\o/
I'm currently working on a signal-capture-and-release device.
 
Okay, I've added 01 and 11 to make 101.
(least-significant bit first)
 
Err, shouldn't 01 and 11 produc- oh, big-endian.
 
It's having a hard time rendering the GIF.
 
My code for that isn't the most efficient.
Would it be possible to golf the adder? :P
 
7:16 PM
As a challenge? I guess.
 
I was more thinking about reducing the space and time it takes.
We can consider the adder to be a block component.
 
Serial adder: goo.gl/pRcuO9 Play it for 131 generations.
 
woooaaahhh...
 
It takes two 2-bt numbers as input and outputs a 3-bit number.
 
Would work for any number of bits though, right?
 
7:21 PM
yes
 
Well, that's pretty awesome!
 
@El'endiaStarman There's really room on the screen to take a 2-bit input and a 3-bit input, but when the output is longer than 3 bits there's not room to display the whole result on screen: goo.gl/SyKtyc
 
Yeah, I did that myself. 11 + 111 -> 0101
What's the block size? 16x16?
Oh, nope, 11x11.
 
Added red corners to show the bounding box of the adder: goo.gl/pMPvA2
For a sense of scale, that 77x66 grid represents 157696 x 135168 GoL cells.
 
Holy moly. :P
 
7:31 PM
I'm not completely certain we will be able to assemble the final computer in a way that is actually runnable.
 
Were we intending to put the whole thing into something like Golly once we're done? Seems like that may be a tad difficult... :P
 
what's the input formt?
 
in The Nineteenth Byte, 25 secs ago, by PhiNotPi
Serial adder that adds 01 + 11 = 101 (least-significant bit first) http://goo.gl/pMPvA2 Instructions for use: type 131 in the text box to the right of "reset," and then click the "slow" button.
 
but where does the binary go?
 
The long wires along the left and right have markers along their sides that point to the places to but the bits.
The output has similar markers to indicate bit positions.
 
7:43 PM
so how could one use the output If it runs longer than 131 generations, the bits just move on
 
@CᴏɴᴏʀO'Bʀɪᴇɴ Well, the output will be directed to some other part of the computer.
 
Oh, I see. (Sorry, I have quite a lot of catching up to do :p I dropped out a while ago and I'm back now)
 
@El'endiaStarman This is more of an understatement than I realized. Even ten frames is taking a while.
 
I can help you make it better if it's in JS
 
It's server-side Python.
Hmm. Actually, maybe part of the problem is client-side...
Yeah, that's it. Failed to load resource: the server responded with a status of 504 (Gateway Timeout) http://play.starmaninnovations.com/varlife/rendergif
The JS code client-side tries to send all of the data at once.
 
7:53 PM
... the 19th byte doesn't seem too enthused with our adder. :/
 
They'll be plenty enthused once we have a full game! [shakes fist]
 
any way I can help?
 
...perhaps. What features were you planning to add for your VarLife extension?
 
lemme open up what I have :p
 
This might be too much to ask, but a gate palette will be immensely helpful: a way to click & drag/rotate gates onto the board from a set of predefined gates.
 
7:59 PM
I was working on something like that
you could save patterns and place them on the board
 
It'd also be pretty awesome to have a way to click-drag sections of the board.
 
give me an example
 
Logisim circuit (contains the adder and a lot of basic building blocks): github.com/PhiNotPi/QuestForTetris/blob/master/comp01.circ
 
Like if there's a gate that's misaligned, then you could draw a box around it and then drag that part.
 
That would also be helpful.
Maybe shift+click+drag to draw perfectly straight lines.
 
8:07 PM
oh, a click-and-drag for moving areas
 
@PhiNotPi Oh that'd be awesome too.
 
lines other than vertical and horizontal?
 
Diagonal lines may be useful.
 
alright
I can write code to do all this, then write a UI
 
If you do that and make it good, I'll add it to my website.
 
8:12 PM
what's the saying "make it work, make it good, make it right"? or something
 
Yeah, Mego's fond of that one.
I could probably vastly improve the gif rendering thing without too much effort. Just re-code the grid updating stuff server-side and send only the initial state, rules, and number of frames.
Could probably vastly improve the gif encoding bit too.
And improve the permalink and implement a URL shortener. :P
 
I'm already working on that
 
Welp. I guess I know what I'm coding today. :P
I think the URL shortener is best done with server-side access so I can store the full URL on the server and fetch it when I get a shortened link.
 
do you have node js?
 
I could.
I think.
 
8:16 PM
it's my "progress" on the extension before I forgot I was doing it
// A box from (uX,uY) upper left to (lX,lY) lower right.
// moves pattern of state cells RIGHT by sX and DOWN by sY.
// m is the mode; default is cell rule, 1 is cell life
vgol.transpose = function transpose(uX,uY,lX,lY,sX,sY,m){
	m = m || 0;
	for(var i=lY;i>=uY;--i){
		for(var j=lX;j>=uY;--j){
			if(typeof grid[i+sY]!=="undefined"&&typeof grid[i+sY][j+sX]!=="undefined"){
				var old = +grid[i+sY][j+sX][m];
				grid[i+sY][j+sX][m] = grid[i][j][m];
				grid[i][j][m] = old;
			}
		}
	}
	updateGraphics();
\o/ I already have a transpose function
 
except the code looks like crap
 
8:32 PM
@El'endiaStarman f*#% the adder is borked.
 
How so?
 
3 hours ago, by PhiNotPi
user image
The line that runs from the first XOR to the first AND, is 1 "unit" too short.
edit: 2 units
The result is that double-carry-overs don't work.
@adipy Hello!
This might be fixable.
 
8:51 PM
It'd be nice to have a tiny delay component, eh?
 
maybe we could write a meta-vgol that is circuits
and then convert that to vgol
 
@CᴏɴᴏʀO'Bʀɪᴇɴ That's be nice.
I'd use it instead of logisim.
 
what's that?
 
A digital circuit simulator: cburch.com/logisim
 
have you ever heard of this? it's very nice, but I'm not sure if it cuts out on what is needed: kolls.net/gatesim
 
8:58 PM
No, I haven't but just on the screenshots it doesn't look as useful as logisim.
 
It's good for simple things
then again, this isn't a simple task :p
 
@CᴏɴᴏʀO'Bʀɪᴇɴ Hmm. Maybe that would be a better project for you, actually. Have tiles that one can place, rotate, and click-and-drag, then simulate how the signals would pass through.
 
ok
I'd need more to go off of tho.
 
@CᴏɴᴏʀO'Bʀɪᴇɴ as in what?
 
well, I don't know precisely what I'd need to, besides tiles that can move and rotate
 
9:07 PM
For each gate, store this information: where the input(s) and output(s) are, and the delay between inputs and outputs. Each tile should be selectable from a bank (probably on the right side or something), and placed on a grid. Then you can click on it to rotate it, or click-and-drag to move it. You'd have to have special input and output tiles so you can set up the initial state and read output. Then you can simulate how the signals will pass through the circuitry.
 
logic gate gates?
 
If we totally standardize tiles, then you just need to know which sides have inputs or outputs (or nothing).
@CᴏɴᴏʀO'Bʀɪᴇɴ Basically, yeah.
 
wait so its not standardized yet?
 
I think all the ones we have are (or can easily be) standardized.
After you get all that, then write a conversion script that produces the permalink for the equivalent VoL circuitry.
 
should I work on this before the UI for vgol?
 
9:11 PM
I personally think so. It'll be a greater help to PhiNotPi, since the current VoL UI is sufficient. Not as awesome as it could be, but good enough.
 
I say, work on this above VoL.
 
We've figured out the gates we need, and now we just need to figure out the circuit components.
Then build an ALU and memory banks. Then implement assembly. Then write assembly. Then write a language built on assembly that actually does the Tetris game. :P
 
one thing at a time :p
which gates specifically?
also, any preferred language?
or would this be an online thing?
 
I was thinking online, and besides, JS is your best lang, so... :P
 
yeah
it's js versus J versus node versus TI-BASIC :p
So, AND, XOR, OR, anything else?
 
9:19 PM
Okay, two AND gates: one with inputs on sides and one with inputs on side and back; two OR gates and two XOR gates with the same configurations; another XOR gate (inputs on side and back) that has two outputs (other side and front); wire crossing; A AND NOT B gate.
 
the back is the top or bottom?
 
Uh, top.
Well, I mean "back" as in "opposite from the one output".
 
oh, right, these things rotate
 
Oh, should also be able to mirror them.
 
alright, so I could implement these gates with those generic properties
 
9:21 PM
Yeah. And they'll all have the same delay and in/out wires will be centered.
I think this tool will be a huge help.
 
is there a tile size, or do I not need to worry about that?
(And I now have my first actual project I can be absorbed in to for the summer :D)
 
@CᴏɴᴏʀO'Bʀɪᴇɴ Well, make them comfortable to use. :P
20x20 pixels is probably good.
 
I was referring to the tile size of the vgol
I guess I don't need to know that though
 
Oh, at the moment they're 11x11.
 
oh, cool
I think I'm going to make each visual tile an html element, a canvas would just be too confounding
 
9:26 PM
Sure, so long as it's not too clunky.
 
"easy to work with" will be my goal
 
I personally would use SVG and some JS library like D3 or Processing or something.
 
I don't know much svg :\
though it might be better for dragging stuff
 
Yeah. I used SVG + D3 for VoL.
SVG is actually pretty simple. It's just a subset of HTML.
 
9:51 PM
yeah, but there's so much stuff :p
 
Just use rect and text for now.
 
gotcha
what should I call it? :p
 
Vgol Circuitry?
 
Or Voltiles.
 
9:54 PM
what does that mean? :p
 
It's just "Vol" + "tiles". There is a similar word: volatile.
 
I knew about that, but I knew you didn't misspell it
I think I'll go with VGoL Circuitry for clarity
 
;-; I don't think there's a way to make (actually functional this time) serial adder with anything less than 4 units between bits (previous was 2).
Unless we create special-purpose micro-circuitry.
 
Isn't that what we've been doing by and large? Creating special-purpose micro-circuitry? :P
 
10:08 PM
yes
 
11:01 PM
@El'endiaStarman I think I got it.
Basically, instead of having to lengthen one wire, I had to shorten another.
goo.gl/fT95Cb (153 generations to solve 11 + 111 = 0101)
@CᴏɴᴏʀO'Bʀɪᴇɴ ^
The downside is that, if we use this design, we're forcing ourselves to use 11x11 gates.
 

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