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1:56 AM
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Q: Can a Von Neumann CPU be pipelined?

gilianzzCan you pipeline a pure Von Neumann architecture based CPU or do you need seperate data and instruction caches for this? If you include seperate instruction and data caches (then it isn't a von neumann CPU anymore, it's a modified Harvard), how do you unify the data of these caches so that they g...

 
If you have separate I and D caches, but they are coherent (writes to the D cache are "seen" by the I cache) then you have a "stored program computer" == "Von Neumann architecture", no?
 
@WanderingLogic: no, technically you have a "modified Harvard architecture".
@WanderingLogic: Since it's a hybrid between the two, you might as well decide to call it "modified von Neumann architecture", but "modified Harvard architecture" is the (much more) established term of art.
 
@RespawnedFluff, the "established term of art"??? I'd say the "established term of art" is to consider it distasteful to call anything a Von Neumann architecture: Patterson&Hennessy, 2/e, 1998, p 33: "...Goldstine distributed the memo and put von Neumann's name on it, much to the dismay of Eckert and Mauchly, whose names were omitted. This memo has served as the basis for the commonly used term von Neumann computer. Several early pioneers in the computer field believe that this term gives too much credit to von Neumman, ..., and too little to ... Eckert & Mauchly ...
... For this reason, the term does not appear elsewhere in this book."
I wonder what would be the term for a single shared 64-bit wide cache but the fetch unit having a 64-bit buffer storing pairs of 32-bit instructions as they are fetched from the cache? How about if the buffer can store an entire cache line?
 
@WanderingLogic: What does that have to do with what I said? Indeed some object to "von Neumann architecture" and call it "Princeton architecture" instead (or nothing at all). But Patterson&Hennessy do mention "Harvard architecture" at least in the more recent versions of their book (albeit in the CD appendinx in the 4th ed.)
 
@RespawnedFluff Yes, in P&H 2e p 35 they say "the term Harvard architecture was coined to describe machines with separate memories. ... this term is used today in a different sense to describe machines with a single main memory but with separate caches for instructions and data."
And then they never use the term again.
And in H&P 4e (the grad level book) the only reference in the index to Harvard Arch is to one of the appendices that is only available online.
 
2:00 AM
@WanderingLogic So what? There are numerous reliable sources which do use the term.
 
@RespawnedFluff You are probably right. What set me off, I think, is that (historically) the distinction is architectural (whether or not the machine supports self modifying code, for example). But caching should be (usually is) invisible to the programmer except from a performance perspective. It's a microarchitectural concept.
 
Are you in Architecture? You've had a lot of nice answers to "systems" type questions lately.
 
2:19 AM
In general, I agree that it's a lot more insightful to say what happens precisely e.g. whether the L1 cache is unified or not, or whether a unified cache is dual ported or not, rather than use vague terms like "modified Harvard architecture". But sometimes the ivy-league terms do get used, so I've that's why I've mentioned them at the end of my answer.
 
2:39 AM
@RespawnedFluff I've seen the term "Princeton" be used for unified I&D, but AFAIK "von Neumann" refers to the architectural feature (of being able to read and write instructions) not any kind of microarchitectural organization.
Which is why I asked the OP for clarification.
 

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