So that means I am not accounting for the base resistance of the transistor Q4 when opening the loop? Also when you say "create a mirror of Q4" do you mean that I should connect to the node between R3 and R4 a complete copy of Q4 and biasing circuitry ?

I tried doing something like this: imgur.com/a/nBWH5D5 Probably not the right way.

@Virgil_T. Yes, when opening the loop between R3 and R4 you disconnect the load which consists of the Q4 input resistance. This load is effective under closed-loop conditions and must be simulated when the loop is open. And yes, the most correct way is to connect a complete copy of the circuitry with Q4 at the opening.

So a complete, correct model of the open loop gain would mean: at the base of Q4 to add the two parallel resistors of the feedback network and a test voltage ac source, while at the other point (where I break the loop) to add the equivalent value of the input resistance of Q4?

No - a mirror of the two parallel resistors at the base of Q4 (where you inject the test signal) is NOT necessary - it will not have any influence on the loop gain (it is just a parallel path to the loop). By the way: The method of (a) using the L-C combination for opening the loop as shown by you and (b) building a complete mirror of the existing load at the opening is a well established method and described in several papers.

Difference being that method a) doesn't account for input impedance of Q4 and method b) does?

I did not speak about two (different) methods - the described method consists of two essential parts: (a) open the loop (ac wise only) and inject a test signal and (b) re-establish the disconnected load.

Only now I have analyzed the test setup as shown in the link (your second comment). It is not correct - what is the purposeof C2 and L2 ? Rememeber: If the loop is closed, the base of Q4 has a DC connection to the two resistors. Hence, the mirror circuit must also directly conncted to the the voltage divider R3-R4.

So direct connection between the copy circuit and the voltage divider. Would the copy circuit still contain the common collector at the end of the circuit, or should I keep only the differential amplifier and its bias circuitry.

This is what I've tried after reading your last comment: imgur.com/a/jzzyCHf . I had included C2 and L2 to bias the copy of the circuit correctly in DC and make it appear in AC when I break the loop in the original circuit.

As the original circuit (closed loop) is biased via R3-R4 you can (should) do the same under open loop conditions,

allaboutcircuits.com/technical-articles/…

As an example: The recommended method is described here:

allaboutcircuits.com/technical-articles/…

So something like this: imgur.com/a/5VXsRYM ?

The copy circuit has the proper bias point and the base of the copy transistor Q2(Q4's copy) is connected at the point I break the loop only when I run the AC analysis.

Yes - I think this looks OK. Did you perform the loop gain simulation?

I performed the open loop ac analysis with the last method and the results were practically the same as those in my first attempt, without the copy circuit and with only the inductor/capacitor combo at the inverting input.

The gain looks ok, no unexpected spikes or anything else. The only weird thing about the Bode plot is that the phase takes weird values: imgur.com/a/neY7pDS

It was just weird to me that it was -180 deg and not 180 deg. But it makes sense if you take 0 deg - (-180deg) to get the phase difference between the input AC test signal and the output.

I was concerned that when and if I wanted to analyze the proper stability of the circuit I would have unusable or weird values for the phase margin

The good part is that this darned assignment doesn't ask any question about the stability of the circuit. I've spent far too much time on this.