@El'endiaStarman I'm not sure if the RS-NOR latch challenge idea would be beneficial for the Tetris efforts.

@PhiNotPi Perhaps, perhaps not. I did consider posing something like wire crossing, but I figured that out way earlier. It's hard to pick something that's not too easy but not too hard either.

Incidentally, how are you planning on doing RAM?

There's two ways to do RAM

first, is that we store words in a grid, 1 bit per cell. We would have an x-bit-wide read bus, and x-bit-wide write bus, and a demultiplexer of some sort to select which address should be written to.

second, is that we store data like the wire-world computer, where data is stored somewhat serially. Each data address is represented by a loop where the data flows around in a circle.

I'm thinking the first option.

Yeah, I was thinking the first option too. I think that kind of RAM is implemented with D-flops.

D-flops seem correct

@El'endiaStarman What kind of architecture would you want?

We could go full x86

@El'endiaStarman ^

...I wonder if I have my notes from that Computer Organization class I took in college...

We could emulate an NES or something and load up the original game.

But seriously though, if we get this thing working, this is like legitimate research-article worthy.

haha, yeah

But seriously though, do you have notes from whatever class?

Was Skyping with fiancée.

Said notes may also be packed up in a box in the storage room.

In any case, they're probably on Wikipedia in one form or another.

@somebody, we have AND, XOR, and OR as shown here (including in the comments), as well as wire crossings.

@El'endiaStarman but... i have an or with just blue and green :(

That still sounds cool. Link/gif?

wait a second

url too long :(

goo.gling

goo.gl/D9Q0w9

latency is probably too long/it might not work work with wires though

Oooh, cool.

I do worry a bit about the second pair of alive cells on the green sheath.

Probably won't be too problematic.

oh

remove green cells on second lowest row?

makes more blue cells going up though

yeah

gates

@El'endiaStarman but it doesn't produce a second green pair

true

By the way, clocks are super easy. There's a lot of periodic configurations of cells.

yeah

Cool that you have a couple, though.

exactly a couple

yep :P

but i'm thinking have each in 9x9 cells

the wire crosser touches the top and bottom edges, might break something in the next cell unless we increase cell size

Yeah, 9x9 might be too small.

I say we hold off on deciding what cell size will be until we're sure we have everything we need.

Oh, a task for you: figure out a better delay mechanism.

I posted one above, but I don't like how clunky it is.

also, we need two-way bends, and all sorts of wire splitters and stuff

because in two-input/two-output gates

Hmm. Not sure if we'll need two-way bends.

I don't plan on using any wires in both directions.

so then two-way bends are really low on the priority list

Pretty much, yeah.

i can work on that

Oh? Okay! What are you planning on using to make it?

just like varlife, just gifs as background

i.e. export the 9x9 tiles

but i'm probably not gonna start for a while

i'm still trying to make varlife easier to use

[nods] That's fine.

then different state changing

actually, you can just have a static gif, then an animated one for each possibility

then you can also have circuit diagram gifs to understand circuits more easilt

yeah

I was thinking of something like what's done with Minecraft redstone diagrams.

btw, my modification is broken - clear/reset doesn't change the svg

okay

btw, i think black = nothing, blue = wire, green = insulation (usually)

how is sr-nor different from wire crossing?

SR-NOR is substantially more complex.

It's gonna require careful timing.

And the question of how to deal with always-on wires.

don't think always-on will be possible

but wires with max electron density should be good enough

Well, we don't have to have a solid output, so to speak. It just has to act sufficiently like it's always on with regards to the gates and such further down the line.

so basically solid output is from a clock with a period of max latency?

I'm not sure what you mean.

solid = 5 cells apart, so the tails don't interfere

mmm, okay

That don't have to be that close together.

if a gate doesn't work with electrons 5 cells apart, increase to 6

Every gate has some latency. An always-on wire would be one that leaves no time between the end of latency and the input coming in.

yeah, i'm saying that sometimes the latency may mean electrons 5 cells apart won't work

right

so basically always on should be produced by a clock, but period should be decided after all vital components

right

And since I think the chances that all components have the same run time + latency is quite low, I think it'll be quite important to have a delay component.

The one I got last night delays signals by 4 ticks.

We'll probably need one that delays by 1 tick.

but

why not just make maximum speed minimum runspeed+latency?

that way there won't be delay components everywhere

hmm

oh, right

And we can shift components to lengthen/shorten wires as needed.

yeah

also, you can shift the cells in the components to make them all have the same runspeed

so, that means many clocks won't work with other components

Clocks are easy.

yeah

so, no perendicular wire crosser that supports simultaneous electrons from both directions yet?

Scroll up to the top.

*three-rule

Eh. I don't think we need to try to do that.

GoL metapixels can simulate any Life-like rule.

so

what else do we need

@El'endiaStarman

*other components

I can't really think of anything particularly crucial.

Do some reading on ALUs and RAM circuitry?

note to self: gate svgs

how should components be selected? dropdown? or tiles + names

also, will svgs be slower then gifs if there are a lot?

*than

I was thinking it'd be best to have static tiles.

We don't need an animation. Just some internal book-keeping to make sure all the timing works out.

so then they light up or something when they are active?

Something like that, sure, but also keep track of how long it takes signals to travel across the tile.

but

not one tick?

Well, we know we have components that work. The hard part is synchronizing them.

they're not already synced?

(apart from latency)

I haven't tried actually putting them together to make a full adder.

so, someone needs to try them, see if they're synced

then make a list somewhere

yeah

You seem eager to try. :)

so

what do i do?

do we need splitters?

so

run speed is 9 for or, and, xor, corner, wire and wires

same as slant

Hello, World! I want someone to help with an adaptation of the rule complex you were discussing to Golly. But I don't know how to program Golly rules in Python. :(

wait

need to test stuff first

same as parallel cross :D that's everything except for perpendicular cross, which i'm sure is the same

latency doesn't matter because tick speed is 1/9

@zyabin101 why python?

@somebody The only scripts in Golly that generate rules are in Python.

but

can't you make the rule file yourself?

(that's what i'm doing right now)

@somebody I can. But I want to give Golly the rule file compilation part because I can't program in Golly's own rule file format, but I can do Python.

@zyabin101 going to dinner, when i get back i'll finish the rule file and put it on pastebin or something

i'm about half finished

@somebody Which version it is? Version with B12/S1 or without?

without

but only because i don't use b12/s1

but it's pretty much the same for all three rules

Also, I found in the comments to the original post a gist with four patterns that contain four simple structures. And look, wire crossing!

?

we already have smaller wire crossing

plus smaller xor/or

not sure if we need a diode to build an ALU/RAM

@zyabin101 try this raw.githubusercontent.com/somebody1234/cellulose/master/…

@somebody I have a GitHub account, and I can somewhat improve this rule file. Can't I?

goo.gl/cK0C3X

@zyabin101 improve how?

@somebody By adding some documentation, and tidying up the rule a bit.

okay

Also I can provide example files.

then you should probably move it into a folder, and put the example files in the 'tetris' folder.

also, verify it with varlife first to see if it works

How do I pull your upstream changes using only the web interface of GitHub? I saw that my fork is one commit short of your repo.

only the web interface?

also, wait a second

it's broken

done

didn't test B12/S1 though

@somebody Okay, how do I pull your upstream changes? Or should I commit the edits myself, effectively losing access to pull requests to your repo?

:( no way to do it via web

help.github.com/articles/syncing-a-fork

git remote add upstream github.com/somebody1234/Misc-Files.git
git fetch upstream
git checkout master
git merge upstream/master

@somebody X(

why can't you use Git Bash/Git GUI?

@somebody I don't want to.

why not?

are you on windows?

@somebody Yes.

github for windows doesn't have an option to merge with upstream?

@somebody I have Windows Vista, which doesn't support GitHub Desktop.

still, why not Git GUI/Git Bash?

if you really don't want to use them, then delete your repo and create a new fork

@somebody No way. XP

why not?

Here is an electron flowing in a wire:

x = 8, y = 7, rule = Tetris
6C2.$B6A.$6C2.$6.A.$5.CAC$5.CAC$5.CAC!

@zyabin101 you can push directly to my repo now

also, changes merged

anyone area51.stackexchange.com/proposals/95772/cellular-automata

Someone does here know why random people visit the room?

@somebody This particular gate can't work because it it 1 tick slower when both of the inputs are 1.

@El'endiaStarman Also, I changed the OR gate so that it uses a B12/S1 cell instead of a B12/S cell. Just to help reduce the number of rules.

I've posted some updates on the sandbox answer.