Here's a function in VHDL:
function func_name(param : param_type; param2 : param2_type) returns return_type is
begin
    -- do some logic
    return some_value;
end function;

-- with-select
with signal select
    value <= some_value when signal_is_this_value,
             other_value when signal_is_other_value,
             last_value when others;
-- when-else
value <= some_value when signal = signal_is_this_value else
         other_value when signal = signal_is_other_value else
         last_value;
-- case-statement -- needs to be in a process:
process(signal)
begin
    case signal is
        when signal_is_this_value => -- do anything, basically
            value <= some_value;

library ieee;
use ieee.std_logic_1664.all;
use ieee.numeric_std.all; -- if you want unsigned or signed numbers

entity entity_name is
    generic(WIDTH : natural := 32)
    port( clock : in std_logic;
          reset : in std_logic;
          d : in std_logic_vector(WIDTH - 1 downto 0);
          q : out std_logic_vector(WIDTH - 1 downto 0));
end entity_name;

library ieee;
use ieee.std_logic_1664.all;
use ieee.numeric_std.all; -- if you want unsigned or signed numbers

entity entity_name is
    generic(WIDTH : natural := 32)
    port( clock : in std_logic;
          reset : in std_logic;
          d : in std_logic_vector(WIDTH - 1 downto 0);
          q : out std_logic_vector(WIDTH - 1 downto 0));
end entity_name;

architecture architecture_name of entity_name is
    signal s1 : type := value;
begin
    -- concurrent statements
    process(sensitivity_list)