**The compilation** process generally has three phases - analyze, **elaborate**, and link - to build an executable (before simulation can be performed). In the elaboration phase, the compiler (i.e. VCS, NC-Verilog, ModelSim, etc.) expands the elements (Verilog code) under generate statements with the respect to the corresponding conditions, iterations, etc. of the generate statements. Generally, these conditional, iterative, etc. generate statements are controlled via module-level parameters; hence giving opportunities to the parent module(s) to configure the instance(s) of the parameterize…