(3) ***Serial Interface***

Pin PD_SCK and DOUT are used for data retrieval, input selection, gain selection and power down controls.

When output data is not ready for retrieval, digital output pin DOUT is high. Serial clock input PD_SCK should be low.

When DOUT goes to low, it indicates data is ready for retrieval.

PD_SCK high min = 0.2uS, max 50uS (1/50uS = 20kHz) (typ 1uS)

PD_SCK low min = 0.2uS (typ 1uS, 1MHz)

By applying 25~27 positive clock pulses at the PD_SCK pin, data is shifted out from the DOUT output pin.

Each PD_SCK pulse shifts out one bit, starting with the MSB bit first, until all 24 bits are shifted out.

The 25th pulse at PD_SCK input will pull DOUT pin back to high.

Input and gain selection is controlled by the number of the input PD_SCK pulses.

PD_SCK clock pulses should not be less than 25 or more than 27 within one conversion period, to avoid causing serial communication error.

PD_SCK Pulses / Input channel Gain

25 clock pulses - select A channel with gain = 128
26 clock pulses - select B channel with gain = 32
27 clock pulses - select A channel with gain = 64