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1:14 AM
@CᴏɴᴏʀO'Bʀɪᴇɴ any luck with a broken keyboard?
 
1:37 AM
Sorry, no. Its just about spread to the entire keyboard. I'll post the source when I can
 
Any clue if you'll get it fixed/replaced any time soon?
(I recognize this project is not necessarily the most urgent thing on your agenda)
 
2:36 AM
What's the best way to do addressing?
Addressing as in: given a binary number N, send some electrons down wire number N.
My vision for RAM is to have a long set of loops (one for each wird) and then addressing is used to send read/write signals to the correct loop.
Here's how the wireworld computer did it: One signal is sent from the "cpu" to the far end of the memory bank, at which point it turns around. After some delay, another signal is send down the memory bank. Those signals eventually meet each other, and the point of collision indicates the desired address. By controlling the delay between signals, the meeting point is changed.
That approach is useful because each action takes constant time, regardless of the address. The downside is that the time taken equals the time for a signal to go all the way to the end of memory and back.
 
 
3 hours later…
5:26 AM
@Phi will get it fixed ASAP :3 coding is my hobby
 
 
7 hours later…
12:38 PM
@El'endiaStarman welcome back!
 
The timing/delay-based addressing might be the simplest.
In part, because calculating the correct delay is as "simple" as creating a countdown timer that's loaded with the address number.
 
For some value of "simple". :P
 
Idea: we could make some special-purpose gates (or a larger circuit) that does the following:
Given an input from the bottom, the circuit passes it out the top. Furthermore, it allows a signal from the left side through to the right side IFF the signal from the bottom matches the type of gate that it is.
There would be two versions: one that allows the left-right signal through only when the bottom input is true, and one that does the same only when the bottom input is false.
Here's how it would be useful: We have a chain of these gates hooked up left-to-right. Then, when a parallel number is supplied at the bottom, then it allows a signal through the chain only if the address matches that particular chain.
 
12:55 PM
I think these could be done with special-purpose gates. Definitely something we should have.
 
The true version would use an AND gate, the false version would use an AND-NOT gate.
 
I was thinking that, but then the bottom-to-top signal passing threw me off.
Though I guess you could just combine a gate and a wire crossing.
 
then we would need a serial-to-parallel converter.
If we had a parallel-to-serial converter, we might be able to make parallel memory as well. (parallel ROM at least)
Unfortunately it seems that the main limit to our computer speed will be memory access.
 
1:19 PM
Parallel to serial ought to be fairly easy - just chain OR gates together.
 
 
4 hours later…
5:03 PM
@El'endiaStarman I'm doing some hardcore adder compaction right now.
 
5:28 PM
@El'endiaStarman @CᴏɴᴏʀO'Bʀɪᴇɴ 2x3 serial adder: goo.gl/cDAORc
It's a significant improvement over the 3x5 I had earlier.
 
....wut. Now that's golfed.
 
It was probably one of the most intense golfing sessions I've had in a while.
 
6:24 PM
an OR gate: goo.gl/V1X2uf the bottom wire can be connected to make double output
 
6:41 PM
I thought we already had OR gates. :P
 
we did, just this is an adjacent-input OR gate that's smaller than the previous version
 
Ahh, okay.
 
 
1 hour later…
7:52 PM
33:11 delay wire goo.gl/0ClIzS
 
Very cool.
 
8:23 PM
I think a 44:11 delay wire will be impossible.
 

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