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8:34 AM
@Gilles I agree with your judgement.
@WanderingLogic That's probably true, too.
 
 
2 hours later…
10:51 AM
@WanderingLogic This one should go to Electrical Engineering, no?
 
@WanderingLogic Dead link.
 
Among many other things the ACM sponsors the International Symposium on Computer Architecture (ISCA) which is occassionaly derisively called the "International Symposium on Cache Architecture."
 
I read the question as "how do Intel and AMD do it on these particular chips?" which would be offtopic.
If there's a conceptual question there, it's ontopic of course.
 
@Raphael Huh. Works for me. It's just a pointer to the ACM computing classification system. (The first major subject is "hardware" and includes caching and pipelining.)
@Raphael The question is literally "How is the L1 cache implemented to support pipelining?"
The Intel i7 and ARM A9 are used as particular references to support the claim that anyone ever talks about pipelining a cache.
(The references are done badly, but still.)
Yes. The question would be on-topic at ee.se.
 
I edited to make it clearer (imho).
I think the question would be better if the OP outlined where they see a problem, but well.
 
11:26 AM
@Raphael Sure. It's not a particularly well worded (or well researched) question, but that doesn't make it more appropriate to dump on ee.se.
I'm perhaps feeling a bit sensitive today.
I think it is extremely likely that the os.se beta will be stopped today due to inactivity.
(Which is not surprising.)
But I think the fact that os.se got to beta demonstrates that cs.se needs to be more receptive to questions that are computer systems related.
Systems is, perhaps, more clearly an engineering discipline than is theory.
 

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